• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.472-477
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• 1987

In order to prevent the short-channel effects due to threshold voltage adjustment implantation in conventional n+ doped silicon gate process, a new approach involving automatic doping of polycide by boron during source and drain implantation is introduced. P-MOSFET devece fabricated by theis approach shows improved short channel characteristics than conventional device with n+ doped gate. Some concerns of adopting this approach in CMOS technology are addressed togetheer with some suggestions.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1197-1199
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• 2009

Self-alignment for the fabrication of printed thin film transistors has become of great interest because of the resolution and registration limits of printing technologies. In this work, self-patterning and selfregistration processes are introduced, which do not need surface energy patterning and the resulting minimum gate channel length could be down to $11.2{\mu}m$ with the sheet resistance of 2.6 ${\Omega}/{\square]$ for the source and drain electrodes.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.875-877
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• 2007

Zinc tin oxide (ZTO) sol-gel solution was synthesized for ink-jet printable semiconducting ink. Bottom-contact type TFT was produced by printing the ZTO layer between the source and drain electrodes. The transistor involving the ink-jet printed ZTO had the $mobility\;{\sim}\;0.01\;cm^2V^{-1}s^{-1}$. We demonstrated the direct-writing of semiconducting oxide for solution processed TFT fabrication.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.841-844
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• 2007

In this paper, a vertical block mura, which massively occurred in the LCD products, was investigated extensively by various methods, source drain (SD) line shift is found out to be one of the key reasons. This work to some extent, establishes theoretic hypothesis for further research and solutions similar issues.

• Transactions on Electrical and Electronic Materials
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• v.16 no.3
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• pp.139-141
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• 2015

Contact resistance of interface between the channel layers and various S/D electrodes was investigated by transmission line method. Different electrodes such as Ti/Au, a-IZO, and multilayer of a-IGZO/Ag/a-IGZO were compared in terms of contact resistance, using the transmission line model. The a-IGZO TFTs with a-IGZO/Ag/a-IGZO of S/D electrodes showed good performance and low contact resistance due to the homo-junction with channel layer.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2007.04a
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• pp.3-4
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• 2007

고분자 반도체를 이용한 유기 박막트랜지스터(OTFT) 소자 제작시 특성 향상을 위해 Self-Assemble Monolayer (SAM)을 이용한 유기 Gate 절연막과 source/drain 전극의 표면처리에 대해 설명하였다. Gate insulator의 경우 소수성 SAM이 고분자 반도체와의 상호작용으로 배열도를 향상시켜 이동도를 증가시켰으며, 전극처리의 경우 접촉저항을 낮추어 injection을 증대시키는 효과를 나타내었다. 각각의 경우 적용되는 SAM 재료와 효과를 극대화시키기 위한 처리공정 전반에 대해 설명하였다.

• Journal of Satellite, Information and Communications
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• v.11 no.4
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• pp.27-32
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• 2016

A conventional double diffused drain n-type MOSFET (DDD_NMOS) device shows SCR behaviors with very low snapback holding voltage and latch-up problem during normal operation. However, a modified DDD_NMOS-based silicon controlled rectifier (DDD_NSCR_CPS) device with a counter pocket source (CPS) structure is proven to increase the snapback holding voltage and on-resistance compare to standard DDD_NSCR device, realizing an excellent electrostatic discharge protection performance and the stable latch-up immunity.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.260-264
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• 2010

In this paper, Ni silicide is formed on boron cluster ($B_{18}H_{22}$) implanted source/drains for shallow junctions of nano-scale CMOSFETs and its thermal stability is improved, using vacuum annealing. Although Ni silicide on $B_{18}H_{22}$ implanted Si substrate exhibited greater sheet resistance than on the $BF_2$ implanted one, its thermal stability was greatly improved using vacuum annealing. Moreover, the boron depth profile, using vacuum post-silicidation annealing, showed a shallower junction than that using $N_2$ annealing.

• Journal of Environmental Impact Assessment
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• v.16 no.2
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• pp.169-176
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• 2007

The paved areas in nonpoint source are highly polluted landuses because of high imperviousness and pollutant mass emissions, such as sand, cereals, and dust from vehicle activities. Most of them in highways are collected by cleaning trucks or discharged to the adjacent soil and water system through the drain ditch in stormwater. Therefore, it is necessary to investigate the relationship between water concentration and total pollutant loadings from the paved areas. From the experiment, CODcr concentration of the cleaning wastewater was 17 times greater than that of the stormwater runoff. Also, concentrations of heavy metals (Cu, Fe, Zn) were 1.3 to 1.5 times higher when compared to the stormwater runoff. While total discharged loadings was insignificant in the cleaning wastewater. In conclusion, these results provide some evidence that the stormwater runoff may be managed carefully to the aspect of total pollutant loadings and the cleaning wastewater may be handled cautiously with the pollutant concentrations in highways.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1789-1791
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• 2007

We fabricated OTFT-OLED display panel by using Ag-paste for source and drains electrode of OTFTs. The OTFTs were fabricated by solution processes such as spin-coating for PVP gate dielectric and screen printing for S/D electrodes with Ag-paste, except pentacene active layer which was deposited by evaporation. The mobility was 0.024 cm2/V.sec , off state current ${\sim}10-11A$, threshold voltage 7.6 V and on/off current ratio ${\sim}105$. The panel consisted of 16 x 16 pixels and each pixel consisted of 2 OTFTs, 1 Capacitor and 1 OLED. The pixels successfully worked in terms of current magnitude supplied to OLED and the control ability of driving and switching OTFTs.