• Proceeding of EDISON Challenge
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• 2013.04a
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• pp.266-268
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• 2013

In this paper, we study the channel doping concentration characteristics of junctionless nanowire transistors (JLT) using Edison nanowire FET device simulation. JLT has no junctions by very simple fabrication process. And this device has less variability and better electrical properties than classical inversion-mode transistors with PN junctions at the source and drain. In this simulation we use tri-gate structure. Source and drain doping concentration is $10^{20}atoms/cm^3$. The simulation results show that I-V characteristics of JLT change due to the variation of channel doping concentration.

• Transactions on Electrical and Electronic Materials
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• v.18 no.3
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• pp.141-143
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• 2017

Novel structured thin film transistors (TFTs) of amorphous silicon zinc tin oxide (a-SZTO) were designed and fabricated with a thin metal layer between the source and drain electrodes. A SZTO channel was annealed at $500^{\circ}C$. A Ti/Au electrode was used on the SZTO channel. Metals are deposited between the source and drain in this novel structured TFTs. The mobility of the was improved from $14.77cm^2/Vs$ to $35.59cm^2/Vs$ simply by adopting the novel structure without changing any other processing parameters, such as annealing condition, sputtering power or processing pressure. In addition, stability was improved under the positive bias thermal stress and negative bias thermal stress applied to the novel structured TFTs. Finally, this novel structured TFT was observed to be less affected by back-channel effect.

• Transactions on Electrical and Electronic Materials
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• v.12 no.6
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• pp.267-270
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• 2011

In the process of inkjet-printed zinc tin oxide thin-film transistor, the effect of metallic interlayer underneath of source and drain electrode was investigated. The reason for the improved electrical properties with thin molybdenum oxide ($MoO_3$) layer was due to the chemically intermixed state of metallic interlayer, aluminum source and drain, and oxide semiconductor together. The atomic configuration of three Mo $3d_3$ and $3d_5$ doublets, three different Al 2p core levels, two Sn $3d_5$, and four different types of oxygen O 1s in the interfaces among those layers was confirmed by X-ray photospectroscopy.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.6
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• pp.462-465
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• 2009

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method, The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than 10), Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.140-140
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• 2010

Non-mass analyzed ion shower doping (ISD) technique with a bucket-type ion source or mass-analyzed ion implantation with a ribbon beam-type has been used for source/drain doping, for LDD (lightly-doped-drain) formation, and for channel doping in fabrication of low-temperature poly-Si thin-film transistors (LTPS-TFT's). We reported an abnormal activation behavior in boron doped poly-Si where reverse annealing, the loss of electrically active boron concentration, was found in the temperature ranges between $400^{\circ}C$ and $650^{\circ}C$ using isochronal furnace annealing. We also reported reverse annealing behavior of sequential lateral solidification (SLS) poly-Si using isothermal rapid thermal annealing (RTA). We report here the importance of implantation conditions on the dopant activation. Through-doping conditions with higher energies and doses were intentionally chosen to understand reverse annealing behavior. We observed that the implantation condition plays a critical role on dopant activation. We found a certain implantation condition with which the sheet resistance is not changed at all upon activation annealing.

• Proceedings of the Korean Geotechical Society Conference
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• 2000.02a
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• pp.32-41
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• 2000

Sand drain as a vertical drainage is widely used in soft ground improvement Recently, sand, the principal source of sand drain, is running out. The laboratory model tests were carried out to utilize gravel as a substitute for sand. Though which the characteristics of gravel are compared to those of sand for engineering purpose. Two cylindrical containers for the model test were filled with marine clayey soil from the west coast of Korea with a column in the center, one with sand, the other with gravel. Vibrating wire type piezometers were installed at the distance of 1.0D, 1.5D and 2.0D from the center of the column. The characteristics of consolidation were studied with data obtained from the measuring instrument place on the surface of the container. The parameter study was performed on the marine clayey soil before and after the test in order to verify the effectiveness of the improvement. The clogging effect was checked at various depth in gravel column after the test. In-situ tests area was divided into two areas by material used. One is Sand Drain(SD) and Sand Compaction Pile(SCP) area, the other is Gravel Drain(GD) and Gravel Compaction Pile(GCP) area. Both areas were monitored to obtain the information on settlement, pore water pressure and bearing capacity by measuring instruments for stage loading caused by embankment. The results of measurements were analyzed. According to the test results, the settlement was found to be smaller in gravel drain than in sand drain. The increase in bearing capacity by gravel pile explains the result. The clogging effect was not found in gravel column. It is assumed that gravel is relatively acceptable as a drainage material. Gravel is considered to be a better material than sand for bearing capacity, and it is found that bearing capacity is larger when gravel is used as a gravel compaction pile than as a gravel drain.

• Proceedings of the Korean Vacuum Society Conference
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• 2003.02a
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• pp.134-134
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• 2003

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.8
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• pp.1-12
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• 2001

The adaptive learning circuit is designed on the basis of modeling of MFSFET (Metal-Ferroelectric-Semiconductor FET) and the numerical results are analyzed. The output frequency of the adaptive learning circuit is inversely proportional to the source-drain resistance of MFSFET and the capacitance of the circuit. The saturated drain current with input pulse number is analogous to the ferroelectric polarization reversal. It indicates that the ferroelectric polarization plays an important role in the drain current control of MFSFET. The output frequency modulation of the adaptive learning circuit is investigated by analyzing the source-drain resistance of MFSFET as functions of input pulse numbers in the adaptive learning circuit and the dimensionality factor of the ferroelectric thin film. From the results, the frequency modulation characteristic of the adaptive learning circuit are confirmed. In other words, adaptive learning characteristics which means a gradual frequency change of output pulse with the progress of input pulse are confirmed. Consequently it is shown that our circuit can be used effectively in the neuron synapses of nueral networks.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.442-446
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• 2000

The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade in response to the constant demand for increased speed, decreased power, and increased parking density. Therefore, it was interested in scaling theory, and full-band Monte Carlo device simulator has been used to study the effects of device scaling on hot carriers in different MOSFET structures. MOSFET structures investigated in this study include a conventional MOSFET with a single source/drain, implant a lightly-doped drain(LDD) MOSFET, and a MOSFET built on an epitaxial layer(EPI) of a heavily-doped ground plane, and those are analyzed using TCAD(Technology Computer Aided Design) for scaling and simulation. The scaling has used a constant-voltage scaling method, and we have presented MOSFET´s characteristics such as I-V characteristic, impact ionization, electric field and recognized usefulness of TCAD, providing a physical basis for understanding how they relate to scaling.

• Journal of Sensor Science and Technology
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• v.20 no.3
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• pp.156-161
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• 2011

We fabricated a schottky barrier metal oxide semiconductor field effect transistor(SB-MOSFET) by applying indium-tin-oxide(ITO) to the source/drain on a highly resistive GaN layer grown on a silicon substrate. The MOSFET, with 10 ${\mu}M$ gate length and 100 ${\mu}M$ gate width, exhibits a threshold gate voltage of 2.7 V, and has a sub-threshold slope of 240 mV/dec taken from the $I_{DS}-V_{GS}$ characteristics at a low drain voltage of 0.05 V. The maximum drain current is 18 mA/mm and the maximum transconductance is 6 mS/mm at $V_{DS}$=3 V. We observed that the spectral photo-response characterization exhibits that the cutoff wavelength was 365 nm, and the UV/visible rejection ratio was about 130 at $V_{DS}$ = 5 V. The MOSFET-type UV detector using ITO, has a high UV photo-responsivity and so is highly applicable to the UV image sensors.