• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.2
• /
• pp.249-254
• /
• 2015

Solution-derived amorphous indium-gallium-zinc oxide (a-IGZO) thin-film-transistor (TFTs) were developed using a microwave irradiation treatment at low process temperature below $300^{\circ}C$. Compared to conventional furnace-annealing, the a-IGZO TFTs annealed by microwave irradiation exhibited better electrical characteristics in terms of field effect mobility, SS, and on/off current ratio, although the annealing temperature of microwave irradiation is much lower than that of furnace annealing. The microwave irradiated TFTs showed a smaller $V_{th}$ shift under the positive gate bias stress (PGBS) and negative gate bias stress (NGBS) tests owing to a lower ratio of oxygen vacancies, surface absorbed oxygen molecules, and reduced interface trapping in a-IGZO. Therefore, microwave irradiation is very promising to low-temperature process.

• ETRI Journal
• /
• v.32 no.6
• /
• pp.932-939
• /
• 2010

In this paper, a fast migration method is proposed. Our method executes local relocation on a model placement where an additional module is added to it for modification with a minimum number of displacements. This method is based on mean-field annealing (MFA), which produces a solution as reliable as a previously used method called simulated annealing. The proposed method requires substantially less time and hardware, and it is less sensitive to the initial and final temperatures. In addition, the solution runtime is mostly independent of the size and complexity of the input model placement. Our proposed MFA algorithm is optimized by enabling module rotation inside an energy function called permissible distances preservation energy. This, in turn, allows more options in moving the engaged modules. Finally, a three-phase cooling process governs the convergence of problem variables called neurons or spins.

• Journal of the Korean Operations Research and Management Science Society
• /
• v.31 no.4
• /
• pp.139-155
• /
• 2006

The facility location problem of this paper is distinguished from the maximal covering location problem and the flxed-charge facility location problem. We propose the maximal profiting location problem (MPLP) that is the facility location problem maximizing profit with multi-product. We apply to the simulated annealing algorithm, the stochastic evolution algorithm and the accelerated simulated annealing algorithm to solve this problem. Through a scale-down and extension experiment, the MPLP was validated and all the three algorithm enable the near optimal solution to produce. As the computational complexity is increased, it is shown that the simulated annealing algorithm' is able to find the best solution than the other two algorithms in a relatively short computational time.

• IE interfaces
• /
• v.18 no.4
• /
• pp.370-381
• /
• 2005

This study is concerned with seeking the optimal allocation(disposition) for maximizing utility of consolidating old fashioned and new air defense weapon system like SAM-X(Patriot missile) and developing efficient solution algorithm based on simulated annealing(SA) algorithm. The SED(selection by effectiveness degree) procedure is implemented with an enhanced SA algorithm in which neighboring solutions could be generated only within the optimal feasible region by using a specially designed PERTURB function. Computational results conducted on the problem sets with a variety of size and parameters shows the significant efficiency of our SED algorithm over existing methods in terms of both the computation time and the solution quality.

• Journal of the Korean Operations Research and Management Science Society
• /
• v.29 no.3
• /
• pp.145-155
• /
• 2004

The design of a communication network has long been a challenging optimization problem. Since the optimal design of a network topology is a well known as a NP-complete problem, many researches have been conducted to obtain near optimal solutions in polynomial time instead of exact optimal solutions. All of these researches suggested diverse heuristic algorithms that can be applied to network design problems. Among these algorithms, a simulated annealing algorithm has been proved to guarantee a good solution for many NP-complete problems. in applying the simulated annealing algorithms to network design problems, generating mechanisms for initial solutions and candidate solutions play an important role in terms of goodness of a solution and efficiency. This study aims at analyzing these mechanisms through experiments, and then suggesting reliable mechanisms.

• Journal of the Institute of Convergence Signal Processing
• /
• v.3 no.1
• /
• pp.87-92
• /
• 2002

Placement is an important step in the physical design of VLSI circuits. It is the problem of placing a set of circuit modules on a chip to optimize the circuit performance. The most popular algorithms for placement include the cluster growth, simulated annealing and integer linear programming. In this paper we propose a stochastic evolution algorithm searching solution space for the placement problem, and then compare it with simulated annealing by analyzing the results of each implementation.

• Journal of Korea Society of Digital Industry and Information Management
• /
• v.17 no.2
• /
• pp.13-20
• /
• 2021

Placement is a very important step in the VLSI physical design process. It is the problem of placing circuit modules to optimize the circuit performance and reliability of the circuit. It is used at the layout level to find strongly connected components that can be placed together in order to minimize the layout area and propagation delay. The most popular algorithms for circuit placement include the cluster growth, simulated annealing, integer linear programming and genetic algorithm. In this paper we propose a adapted genetic algorithm searching solution space for the placement problem, and then compare it with simulated annealing and genetic algorithm by analyzing the results of each implementation. As a result, it was found that the adaptive genetic algorithm approaches the optimal solution more effectively than the simulated annealing and genetic algorithm.

• Transactions on Electrical and Electronic Materials
• /
• v.13 no.5
• /
• pp.241-244
• /
• 2012

Antimony doped tin oxide (ATO) thin films on glass substrate were prepared by the chemical solution deposition (CSD) method, using sol-gel solution synthesized by non-alkoxide precursors and the sol-gel route. The crystallinity and electrical properties of ATO thin films were investigated as a function of the annealing condition (both annealing environments and temperatures), and antimony (Sb) doping concentration. Electrical resistivity, carrier concentration, Hall mobility and optical transmittance of ATO thin films were improved by Sb doping up to 5~8 mol% and annealing in a low vacuum atmosphere, compared to the undoped tin oxide counterpart. 5 mol% Sb doped ATO film annealed at $550^{\circ}C$ in a low vacuum atmosphere showed the highest electrical properties, with electrical resistivity of about $8{\sim}10{\times}10^{-3}{\Omega}{\cdot}cm$, and optical transmittance of ~85% in the visible range. Our research demonstrates the feasibility of low-cost solution-processed transparent conductive oxide thin films, by controlling the appropriate doping concentration and annealing conditions.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.28 no.8
• /
• pp.481-485
• /
• 2015

We investigated the effects of annealing on the electrical and thermal properties of ZTO/4H-SiC heterojunction diodes. A ZTO thin film layer was grown on p-type 4H-SiC substrate by using solution process. The ZTO/SiC heterojunction structures annealed at $500^{\circ}C$ show that $I_{on}/I_{off}$ increases from ${\sim}5.13{\times}10^7$ to ${\sim}1.11{\times}10^9$ owing to the increased electron concentration of ZTO layer as confirmed by capacitance-voltage characteristics. In addition, the electrical characterization of ZTO/SiC heterojunction has been carried out in the temperature range of 300~500 K. When the measurement temperature increased from 300 K to 500 K, the reverse current variation of annealed device is higher than as-grown device, which is related to barrier height in the ZTO/SiC interface. It is shown that annealing process is possible to control the electrical characteristics of ZTO/SiC heterojunction diode.

• Journal of Powder Materials
• /
• v.24 no.2
• /
• pp.102-107
• /
• 2017

Porous polytetrafluoroethylene (PTFE) thin films are fabricated by spin-coating using a dispersion solution containing PTFE powders, and their crystalline properties are investigated after thermal annealing at various temperatures ranging from 300 to $500^{\circ}C$. Before thermal annealing, the film is densely packed and consists of many granular particles 200-300 nm in diameter. However, after thermal annealing, the film contains many voids and fibrous grains on the surface. In addition, the film thickness decreases after thermal annealing owing to evaporation of the surfactant, binder, and solvent composing the PTFE dispersion solution. The film thickness is systematically controlled from 2 to $6.5{\mu}m$ by decreasing the spin speed from 1,500 to 500 rpm. A triboelectric nanogenerator is fabricated by spin-coating PTFE thin films onto polished Cu foils, where they act as an active layer to convert mechanical energy to electrical energy. A triboelectric nanogenerator consisting of a PTFE layer and Al metal foil pair shows typical output characteristics, exhibiting positive and negative peaks during applied strain and relief cycles due to charging and discharging of electrical charge carriers. Further, the voltage and current outputs increase with increasing strain cycle owing to accumulation of electrical charge carriers during charge-discharge.