Design and Implementation of a Stochastic Evolution Algorithm for Placement

Placement 확률 진화 알고리즘의 설계와 구현

  • 송호정 (충북대학교 컴퓨터공학과·컴퓨터정보통신연구소) ;
  • 송기용 (충북대학교 컴퓨터공학과·컴퓨터정보통신연구소)
  • Published : 2002.01.01

Abstract

Placement is an important step in the physical design of VLSI circuits. It is the problem of placing a set of circuit modules on a chip to optimize the circuit performance. The most popular algorithms for placement include the cluster growth, simulated annealing and integer linear programming. In this paper we propose a stochastic evolution algorithm searching solution space for the placement problem, and then compare it with simulated annealing by analyzing the results of each implementation.

배치(Placement)는 VLSI 회로의 physical design에서 중요한 단계로서 회로의 성능을 최대로 하기 위하여 회로 모듈의 집합을 배치시키는 문제이며, 배치 문제에서 최적의 해를 얻기 위해 클러스터 성장(cluster growth), 시뮬레이티드 어닐링(simulated annealing; SA), ILP(integer linear programming)등의 방식이 이용된다. 본 논문에서는 배치 문제에 대하여 확률 진화 알고리즘(stochastic evolution algorithm; StocE)을 이용한 해 공간 탐색(solution space search) 방식을 제안하였으며, 제안한 방식을 시뮬레이티드 어닐링 방식과 비교, 분석하였다.

Keywords

References

  1. VLSI Physical Design Automation Theory and Practice S. M. Sait, H. Youssef
  2. Algorthms for VLSI Physical Design Automation. 3rd Edition Naveed A. Sherwani
  3. IEEE Transaction on Computer-Aided Design ON Extending Slicing Floorplan to Handle L/T-Shaped Modules and Abutment constraints F.Y. Young, D.F. Wong, Hannah H. Yang
  4. Stochastic evolution: A fast effective heuristic for some generic layout problems. 17th ACM/IEEE Design Automation Conference Y.Saab;V.Rao.
  5. Science v.220 no.4598 Optimization by Simulated Annealing S. Kirkpatrick, C. D. Gelatt;M. P. Vecchi
  6. Iterative Computer Algorithms with Applications in Engineering Computer Society S. M. Sait, H. Youssef
  7. VLSI cell placement techniiques. ACM Computing Surveys v.23 no.2 K.Shahookar;P.Mazumder.
  8. A new algorithm for floorplanning design. Proc. of the 23rd DAC D.F.Wong;C.L.Liu
  9. Proceedings of 23rd Deisgn Automation Conference Timberwolf3.2: A new standard cell plancement and global routing package. C.Sechen;A.L.Sangiovanni-Vincentelli
  10. IEEE Transactions on CAD v.15 VLSI module placement based on rectangle-packing by the sequene-pair. H.Murata, K.Fujiyoshi, S.Nakatake,;Y.Kajitani.
  11. IEEE Transactions on CAD v.10 no.12 A new method for flpoorplanning using topological constraint reduction. G.Vijayan;R.Tasy.