• Journal of electromagnetic engineering and science
• /
• v.11 no.4
• /
• pp.282-289
• /
• 2011

GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.13 no.7
• /
• pp.633-640
• /
• 2002

In this paper, the small chip meander antenna for dual-frequency operation is presented. The proposed chip meander antennas was fabricated by the ceramic chip using LTCC-MLC process. It is a novel compact dual-frequency design using a meandered patch that achieves more degrees of freedom for adjusting dual-frequency operation and the size reduction with narrow frequency ratio. And it is proposed that the 3D structure for additional size reduction of the meander antenna. The size reduction of the 3D meander antenna is as large as 50 % as compared to the design for dual-frequency operation not using 3D structure. It is observed that the principle of dual-frequency operation through current distribution, return loss and radiation pattern.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.13 no.10
• /
• pp.840-846
• /
• 2000

In this work, small-size, high-performance solenoid-type RF chip inductors utilizing a low-loss Al$_2$O$_3$core material were investigated. The size of the chip inductors fabricated in this work were 15$\times$10$\times$0.7㎣, 2.1$\times$1.5$\times$10㎣, and 2.4$\times$2.0$\times$1.4㎣ and copper (Cu) wire with 40 ㎛ diameter was used as the coils. High frequency characteristics of the inductance, quality factor, and impedance of developed inductors were measured suing an RF Impedance/Material Analyzer (HP4291B with HP16193A test fixture). It was observed that the developed inductors with the number of turns of 7 have the inductance of 33 to 100nH and exhibit the self-resonant frequency (SRF) of .26 to 1.1 GHz. The SRF of inductors decreases with increasing the inductance and the inductors have the quality factor of 60 to 80 in the frequency range of 300 MHz to 1.1 GHz. In this study, small-size solenoid-type RF chip inductors with high inductance and high quality factor were fabricated successfully. It is suggested that the thin film-type inductor is necessary to fabricate the smaller size inductors at the expence of inductance and quality factor values.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2002.11a
• /
• pp.131-135
• /
• 2002

In this project, we have developed various techniques for subminiaturization, surface implementation, high frequency design, small-sizes SMD, performance test and applications of ultra small chip antenna, which is a core component for the personal communication systems. We also obtained base techniques for the next-generation ultra small chip antenna design and fabrication techniques for an internationally competitive subminiature ultra small chip antenna. Center frequency is 2442.5MHz(Type), return loss is -10dB max, VSWR is 2max, xy max gain is -2dB min, size is 0.05ccmax.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.17 no.3
• /
• pp.340-347
• /
• 2004

Ultra-small size, high-performance, solenoid-type RF chip inductors utilizing low-loss A1$_2$O$_3$ core materials were investigated. The dimensions of the RF chip inductors fabricated were 1.0mm${\times}$0.5mm${\times}$0.5mm and copper coils were used. The materials (96％ A1$_2$O$_3$) and shape (I-type) of the core, the diameters (40${\mu}{\textrm}{m}$) and position (middle) of the coil, and the lengths (0.35mm) of solenoid were determined by a high-frequency structure simulator (HFSS) to maximize the performance of the inductors. The high-frequency characteristics of the inductance (L) and quality-factor (Q) of the developed inductors were measured using a RF impedance/material analyzer (E4991A with E16197A test fixture). The developed inductors exhibit an inductance of 11 to 11.3nH and a qualify factor of 22.3 to 65.7 over the frequency ranges of 250 MHz to 1.7 GHz, and show results comparable to those measured for the inductors prepared by Coilcraft$^{TM}$. The simulated data described the high-frequency data of the L and Q of the fabricated inductors well.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.1
• /
• pp.28-36
• /
• 2010

Hardware implementation methods for Artificial Neural Network (ANN) have been researched for a long time to achieve high performance. We have proposed a Network on Chip (NoC) for ANN, and this architecture can reduce communication load and increase performance when an implemented ANN is small. In this paper, a multiple NoC models are proposed for ANN, which can implement both a small size ANN and a large size one. The simulation result shows that the proposed multiple NoC models can reduce communication load, increase system performance of connection-per-second (CPS), and reduce system running time compared with the existing hardware ANN. Furthermore, this architecture is reconfigurable and reparable. It can be used to implement different applications of ANN.

• ETRI Journal
• /
• v.27 no.2
• /
• pp.133-139
• /
• 2005

A monolithic microwave integrated circuit (MMIC) chip set consisting of a power amplifier, a driver amplifier, and a frequency doubler has been developed for automotive radar systems at 77 GHz. The chip set was fabricated using a 0.15 ${\mu}$ gate-length InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (mHEMT) process based on a 4-inch substrate. The power amplifier demonstrated a measured small signal gain of over 20 dB from 76 to 77 GHz with 15.5 dBm output power. The chip size is 2mm${\times}$ 2mm. The driver amplifier exhibited a gain of 23 dB over a 76 to 77 GHz band with an output power of 13 dBm. The chip size is 2.1mm${\times}$ 2mm. The frequency doubler achieved an output power of -6 dBm at 76.5 GHz with a conversion gain of -16 dB for an input power of 10 dBm and a 38.25 GHz input frequency. The chip size is 1.2mm ${\times}$ 1.2mm. This MMIC chip set is suitable for the 77 GHz automotive radar systems and related applications in a W-band.

• Journal of the Korean Wood Science and Technology
• /
• v.43 no.2
• /
• pp.186-195
• /
• 2015

This study aims at modeling the rotary drying of wood chips in co-current mode and estimating the drying time of larch (Larix kaemferi) wood chip. Drying data were obtained in a lab. scale fixed bed dryer operating with an air velocity of 1 m/sec. and at hot air inlet temperatures of $100^{\circ}C$, $200^{\circ}C$, and $300^{\circ}C$. The lab. scale fixed-bed drying rates for small, medium and large size larch wood chips that had been dried from 40% wet-based moisture content (MC) to 10% MC at $200^{\circ}C$ drying temperature were 17.3 %/min., 10.2 %/min. and 5.5 %/min., respectively. It was predicted that larch large size wood chips could be dried from 40% MC to 10% MC in about 23.0, 34.6, and 44.7 minutes at $300^{\circ}C$, $200^{\circ}C$ and $150^{\circ}C$, respectively. Expected drying times for medium size chips were about 8.6, 11.2 and 13.2 minutes and those for small size chips were 4.3, 5.5 and 6.4 minutes, respectively.

• Proceedings of the International Microelectronics And Packaging Society Conference
• /
• 2000.10a
• /
• pp.39-45
• /
• 2000

A small camera module fabricated by including bare chip bonding methods is utilized to realize advanced mobile devices. One of the driving forces is the TOG (Tape On Glass) bonding method which reduces the packaging size of the image sensor clip. The TOG module is a new thinner and smaller image sensor module, using flip chip interconnection method with the ACP (Anisotropic Conductive Paste). The TOG production process was established by determining the optimum bonding conditions for both optical glass bonding and image sensor clip bonding lo the flexible PCB. The bonding conditions, including sufficient bonding margins, were studied. Another bonding method is the flip chip bonding method for DSP (Digital Signal Processor) chip. A new AC\ulcorner was developed to enable the short resin curing time of 10 sec. The bonding mechanism of the resin curing method was evaluated using FEM analysis. By using these flip chip bonding techniques, small camera module was realized.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.05a
• /
• pp.681-684
• /
• 2008

In this paper, triple band mobile chip antenna for DCS($1.71{\sim}1.88GHz$) / PCS($1.75{\sim}1.87GHz$) / UPCS($1.85{\sim}1.99GHz$) on PCB Layout is fabricated. As designed and fabricated antenna is loaded PCB layout, that plate a both side at two independence patterns(upper & lower) to reduce the size and a capacitor for DCS, PCS, UPCS band is proposed. The antenna has a small size of about $19mm{\times}4mm{\times}1.6mm$, narrow bandwidth which is the defect of chip antenna is improved. Bandwidth of fabricated antenna to VSWR less than 2 is satisfied and all bandwith is acquired 15.1 % at $1.71GHz{\sim}1.99GHz$.