• Journal of Biomedical Engineering Research
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• v.28 no.3
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• pp.423-428
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• 2007

Programmable FIR filters are used in various signal processing tasks in medical ultrasound imaging, which are one of the major factors increasing hardware complexity. A widely used method to reduce the hardware complexity of a programmable FIR filter is to encode the filter coefficients in the canonic signed digit (CSD) format to minimize the number of nonzero digits (NZD) so that the multipliers for each filter coefficients can be replaced with fixed shifters and programmable multiplexers (PM). In this paper, a new structure for programmable FIR filters with a improved frequency response and a reduced hardware complexity compared to the conventional shift-and-add architecture using PM is proposed for implementing a very small portable ultrasound scanner. The CSD codes are optimized such that there exists at least one common nonzero digit between neighboring coefficients. Such common digits are then implemented with the same shifters. For comparison, synthesisable VHDL models for programmable FIR filters are developed based on the proposed and the conventional architectures. When these filters have the same hardware complexity, pass-band ana stop-band ripples of the proposed filter are lower than those of the conventional filter by about $0.01{\sim}0.19dB$ and by about $5{\sim}10dB$, respectively. For the same filter performance, the hardware complexity of the proposed architecture is reduced by more than 20% compare to the conventional SaA architecture.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.1
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• pp.157-165
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• 2013

In this paper, efficient digit-serial VLSI architecture for 1D (9,7) lifting-based discrete wavelet transform (DWT) filter has been proposed. The proposed architecture computes the DWT in digit basis, so that the required hardware is reduced. Also, the multiplication is replaced with the shift and add operation to minimize the hardware requirement. Bit allocation for input, output, and the internal data has been determined by analyzing the PSNR. We have carefully designed the data feedback latency not to degrade the performance in the recursive folded scheduling. The proposed digit-serial architecture requires small amount of hardware but achieve 100% of hardware utilization, so we try to optimize the tradeoffs between the hardware cost and the performance. The proposed architecture has been designed and verified by VerilogHDL and synthesized by Synopsys Design Compiler with a DongbuHitek $0.18{\mu}m$ STD cell library. The maximum operating frequency is 330MHz with 3,770 gates in equivalent two input NAND gates.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.12
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• pp.1609-1617
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• 2019

Described in this paper is a design of hardware accelerator for implementing public-key cryptographic protocols (PKCPs) based on Elliptic Curve Cryptography (ECC) and RSA. It supports five elliptic curves (ECs) over GF(p) and three key lengths of RSA that are defined by NIST standard. It was designed to support four point operations over ECs and six modular arithmetic operations, making it suitable for hardware implementation of ECC- and RSA-based PKCPs. In order to achieve small-area implementation, a finite field arithmetic circuit was designed with 32-bit data-path, and it adopted word-based Montgomery multiplication algorithm, the Jacobian coordinate system for EC point operations, and the Fermat's little theorem for modular multiplicative inverse. The hardware operation was verified with FPGA device by implementing EC-DH key exchange protocol and RSA operations. It occupied 20,800 gate equivalents and 28 kbits of RAM at 50 MHz clock frequency with 180-nm CMOS cell library, and 1,503 slices and 2 BRAMs in Virtex-5 FPGA device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.404-406
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• 2015

This paper describes a small-area hardware implementation of the block cipher algorithm CLEFIA-128 which supports for 128-bit master key. A compact structure using single data processing block is adopted, which shares hardware resources for round transformation and the generation of intermediate values for round key scheduling. In addition, data processing and key scheduling blocks are simplified by utilizing a modified GFN(generalized Feistel network) and key scheduling scheme. The CLEFIA-128 crypto-processor is verified by FPGA implementation. It consumes 823 slices of Virtex5 XC5VSX50T device and the estimated throughput is about 105 Mbps with 145 MHz clock frequency.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1698-1705
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• 2016

In this paper, a hardware-in-the-loop simulation platform for MMCs is established, which connects a real time digital simulator (RTDS) and a designed MMC controller with optical fiber. In this platform, the converter valves are simulated with a small time step of 2.5 microsecond in the RTDS, and multicore technology is implemented for the controller so that the parallel valve control is distributed between different cores. Therefore, the designed controller can satisfy the requirements of real-time control. The functions of the designed platform and the rationality for the designed controller are verified through experimental tests. The results show that different modulation modes and various control strategies can be implemented in the simulation platform and that each control objective can been tracked accurately and with a fast dynamic response.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.1
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• pp.76-89
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• 2013

In this paper, we propose a novel optical fault detection scheme for RSA hardware based on Montgomery exponentiation, which can effectively detect optical fault injection during the exponent calculation. To protect the RSA hardware from the optical fault injection attack, we implemented integrity check logic for memory and optical fault detection logic for Montgomery-based multiplier. The proposed scheme is considered to be safe from various type of attack and it can be implemented with no additional operation time and small area overhead which is less than 3%.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.4 no.1
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• pp.34-39
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• 2004

Huffman coding which has been used in many data compression algorithms is a popular data compression technique used to reduce statistical redundancy of a signal. It has been proposed that the Huffman algorithm can decode efficiently using characteristics of the Huffman tables and patterns of the Huffman codeword. We propose a new Huffman decoding algorithm which used a multi way tree search and present an efficient hardware implementation method. This algorithm has a small logic area and memory space and is optimized for high speed decoding. The proposed Huffman decoding algorithm can be applied for many multimedia systems such as MPEG audio decoder.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.9
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• pp.1497-1503
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• 2016

This paper presents the overall measurement system for on-line test of super-speed maglev train. The super-speed maglev train is composed of vehicle, propulsion, power, and so on. In order to evaluate and diagnose for sub-system, we made overall measurement system. Just like the other measurement system, it is designed to distributed type. The hardware is consist of SCXI, PXI, Terminal, UPS, and so forth. It is installed on a train, control room, power room and track to collect lots of signals. The software controls hardware system, monitors main data such as inverter current, converter voltage. Using the measurement system, we evaluated a lot of performances for vehicle, track, and so forth. Through the developed system have improved reliability and safety for super-speed maglev train.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.10-21
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• 1998

In this paper, we analyze the problems of conventional and previous mehtod on delay test method in IEEE 1149.1. To solve them, we propose two kinds of delay test architectures. One is called ARCH-C, is for combinatonal circuit, and the other is ARCH-S, for clocked sequential circuit. ARCH-C is able to detect delay defect of 0.5 $T_{tck}$ or 1 $T_{tck}$ size. And ARCH-C have a fixed and small amount of hardware overhead, on the contrary preious method has a hardware overhead on the dependent of CUT. This paper discusses weveral problems of Delay test on IEEE 1149.1 for clocked sequential circuit. We suggest the method called ARCH-S, is based on a clock counting technique to generate continuous clocked input of CUT. the simulation results ascertain the accurate operation and effectiveness of the proposed architectures.res.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.936-939
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• 2002

FPCA is the necessary device to design of hardware at present, it is researched on many ways of applying to design caused by expansion of capacity in recent years. One of these applying ways is SoC (System on a Chip) that is proposed for realizing the basic function of a system. For realizing SoC efficiently, IP (Intellectual property) is very important and developed for re-use of hardware. A MPU for built-in exists as an IP. But almost of MPUs at present as an IPs are lengthy and large-scale for using embedded-application. Furthermore, the function of executing specific treatment critically is required to embedded MPU. We propose a flexible and small scale MPU and its design method.