• Proceedings of the KSME Conference
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• 2000.11b
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• pp.556-561
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• 2000

Comprehensive numerical computations are made of side-heated squire cavity which is exposed to time dependent external mechanical forcing. Numerical solutions are acquires to the governing two-dimensional Navier-Stokes equations for a Boussinesq fluid. Time dependent heat transfer characteristics of interior fluid are analyzed to illustrate resonance phenomenon. When system is exposed to pure sinusoidal mechanical forcing, the numerical results disclose that the basic mechanism of resonance of mechanical forcing is same as that of thermal forcing of Ref. [3, 9]. In comparatively small amplitude of mechanical forcing, thermal characteristics of the system are similar to basic system(${\varepsilon}=0$).

• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.2
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• pp.380-388
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• 1994

Study on the chaotic stirring has been performed numerically and experimentally for a shallow rectangular tank accompanying a vortex shedding. The model is composed of a rectangular tank with a vertical plate with a length half the width of the tank. The tank is subject to a horizontal sinusoidal oscillation. The chaotic stirring was analysed by Poincare sections, unstable manifolds and Lyapunov exponents. As Reynolds number is increased the stirring effect is decreased due to the growth of a regular regions near the lower surface of the tank. In the other hand decrease of Reynolds number gives a weaker vortex shedding resulting in the poorer stirring effect. It was also found that the Lyapunov exponent is the highest at the dimensionless period of 1.3-1.5, which seems to be the best condition for the efficient stirring. The experimental visualization for the deformation of materials exhibits the striation pattern similar to the unstable manifold obtained numerically.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.5
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• pp.527-534
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• 1987

Two phase voltage controlled oscillation was realized by using the Electronic analog simulation of nonlinear simultaneous 2st order equation in terms of vibration and it's usefullness was sustined. Sinde it is complex and expensive to implement the circuits actually which composits and multiplicate the two phase signal squared respectively, this paper is obtained the simplificotion and switching circuit. The circuit introducced in this paper had propotionality of frequency to control input voltage, rapid response time, and little phase error, also this circuit operated with very low THD(Total Harmonic Distortion) and constant amplitude at higher than 10 :1 of frequency ratio.

• Journal of Industrial Technology
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• v.11
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• pp.43-53
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• 1991

Two kinds of simple active oscillators are proposed and analyzed assuming that operational amplifier has two-poles frequency characteristics. The first circuit is composed of one operational amplifier, one resistor and one grounded capacitor. The second oscillator is realized with one operational amplifier and three resitors. Proposed oscillators have the low sensitivity of the oscillation frequency for little variations of the passive element values. By the experimental results obtained with Op-Amp. ${\mu}A741$, the simple oscillators can be useful for the frequency range $1.25 KHz{\leq}f_{01}{\leq}40KHz$ for the active-RC type or $45.45 KHz{\leq}f_{02}{\leq}400KHz$ for the active-R oscillator, and it is shown to transform the active-R oscillator circuit into the voltage controlled type. Therefore, two kinds of oscillator circuit are attractive for the IC realization, because they have one operational amplifier, one resistor and one grounded capacitor, or three resistors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.4
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• pp.65-73
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• 2003

This paper presents the implementation of an analog signal-processing ASIS to detect an angular velocity signal from a vibrator angular velocity detection sensor. The output of the sensor to be charge appeared as the variation of the capacitance value in the structure of the sensor was detected using charge amplifiers and a self oscillation circuit for driving the sensor was implemented with a sinusoidal self oscillation circuit using the resonance characteristics of the sensor. Specially an automatic gain control circuit was utilized to prevent the deterioration of self-oscillation characteristics due to the external elements such as the characteristic variation of the sensor process and the temperature variation. The angular velocity signal, amplitude-mod)Hated in the operation characteristics of the sensor, was demodulated using a synchronous detection circuit. A switching multiplication circuit was used in the synchronous detection circuit to prevent the magnitude variation of detected signal caused by the amplitude variation of the carrier signal. The ASIC was designed and implemented using 0.5${\mu}{\textrm}{m}$ CMOS process. The chip size was 1.2mm x 1mm. In the experiment under the supply voltage of 3V, the ASIC consumed the supply current of 3.6mA and noise spectrum density from dc to 50Hz was in the range of -95 dBrms/√Hz and -100 dBrms/√Hz when the ASIC, coupled with the sensor, was in normal operation.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.955-959
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• 2003

A technique for realizing linear phase IIR filters has been proposed by Powell-Chau which gives a real-time implementation of H(z-1).H(z), where H(z) is a causal nonlinear phase IIR filter. Powell-Chau system is linear but not timeinvariant system. Therefore, that system has group delay response that exhibits a minor sinusoidal variation superimposed on a constant value. In the signal processing, this oscillation seriously degrade the signal quality. Unfortunately, that system has a large sample delay of 4L and also more computational complexity. Proposed system is present a reduced computational complexity technique by moved the numerator polynomial of H(1/z) out to cascade with causal filter H(z) and remain only all-pole of H(1/z), then applied truncated infinite impulse response to finite with truncated IIR filtel $H_L$(z) and L sample delay to subtract the output sequence from the top and bottom filter. Proposed system is linear time invariance and group delay response and total harmonic distortion are also improved.

• Proceedings of the KIEE Conference
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• 1991.07a
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• pp.611-614
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• 1991

In variable speed driving system of three phase induction motor controlled by an inverter, because of the switching of semiconductor devices in inverter, an appreciable amount of harmonic components of voltage waveform can cause the motor to generate losses, torque ripple, acoustic noise and oscillation of semiconductor devices. In this paper a new PAM type PWM inverter using IGBT is described. The output waveforms in the proposed PAM type PWM inverter are investigated both theoretiically and experimentally. The line-voltage waveform is composed of fundamental component and the sidebands of carrier frequency. The lower order harmonics are not included in the output wave form. As each inverter arm does not operate during two-thirds period, the heats, generated in the devices are reduced. That is, the size of the inverter system can he minimized because of the reduction in the heat dissipating equipment.

• Transactions of the Korean Society of Mechanical Engineers
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• v.17 no.8
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• pp.2122-2130
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• 1993

A numerical and experimental study has been performed on the flow in a shallow rectangular tank accompanying a vortex shedding. The model is composed of a rectangular tank with a vertical plate with a length half the width of the tank. The tank is subject to a horizontal sinusoidal oscillation. The numerical analysis shows that the pattern of vortex shedding changes considerably when the Reynolds number $R_e$ is varied from 500 to 7500. It is symmetric for $R_e$ <1500 and asymmetric for $R_e$ > 1500. The kinetic energies of the right-hand and left-hand sides of the vertical plate are used to quantify the degree of the asymmetry. Experimental visualization is carried out at $R_e$ = 3876 and 52000. The development of the streamline pattern at $R_e$ = 3876 is in closer agreement with the numerical result at $R_e$ = 1000 than that at $R_e$ =3876. The asymmetric pattern is observed at $R_e$ = 52000.

• Journal of Electrical Engineering and Technology
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• v.10 no.5
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• pp.1989-2000
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• 2015

In this paper, digital peak current mode control for single phase H-bridge inverters is developed and implemented. The digital peak current mode control is achieved by directly controlling the PWM signals by cycle-by-cycle current limitation. Unlike the DC-DC converter where the output voltage always remains in the positive region, the output of DC-AC inverter flips from positive to negative region continuously. Therefore, when the inverter operates in negative region, the control should be changed to valley current mode control. Thus, a novel control logic circuit is required for the function and need to be analyzed for the hardware to track the sinusoidal reference in both regions. The problem of sub-harmonic instability which is inherent with peak current mode control is also addressed, and then proposes the digital slope compensation in constant-sloped external ramp to suppress the oscillation. For unipolar PWM switching method, an adaptive slope compensation in digital manner is also proposed. In this paper, the operating principles and design guidelines of the proposed scheme are presented, along with the performance analysis and numerical simulation. Also, a 200W inverter hardware prototype has been implemented for experimental verification of the proposed controller scheme.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1543-1546
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• 2002

The expandable 4 bit adder/subtracter IC was designed using the adiabatic and dynamic CMOS logic (ADCL) circuit as the ultra-low power consumption basic logic circuit and the IC was fabricated using a standard 1.2 ${\mu}$ CMOS process. As the result the steady operation of 4 bit addition and subtraction has been confirmed even if the frequency of the sinusoidal supply voltage is higher than 10MHz. Additionally, by the simulation, at the frequency of 10MHz, energy consumption per operation is obtained as 93.67pJ (ar addition and as 118.67pJ for subtraction, respectively. Each energy is about 1110 in comparison with the case in which the conventional CMOS logic circuit is used. A simple and low power oscillation circuit is also proposed as the power supply circuit f3r the ADCL circuit. The oscillator operates with a less one volt of DC supply voltage and around one milli-watts power dissipation.