• 대한수학회보
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• 제60권5호
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• pp.1181-1199
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• 2023

For solving complex symmetric positive definite linear systems, we propose a single step real-valued (SSR) iterative method, which does not involve the complex arithmetic. The upper bound on the spectral radius of the iteration matrix of the SSR method is given and its convergence properties are analyzed. In addition, the quasi-optimal parameter which minimizes the upper bound for the spectral radius of the proposed method is computed. Finally, numerical experiments are given to demonstrate the effectiveness and robustness of the propose methods.

• Journal of Information Processing Systems
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• 제10권4호
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• pp.523-542
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• 2014

One-dimensional arrays with subscripts formed by induction variables in real programs appear quite frequently. For most famous data dependence testing methods, checking if integer-valued solutions exist for one-dimensional arrays with references created by induction variable is very difficult. The I test, which is a refined combination of the GCD and Banerjee tests, is an efficient and precise data dependence testing technique to compute if integer-valued solutions exist for one-dimensional arrays with constant bounds and single increments. In this paper, the non-continuous I test, which is an extension of the I test, is proposed to figure out whether there are integer-valued solutions for one-dimensional arrays with constant bounds and non-sing ularincrements or not. Experiments with the benchmarks that have been cited from Livermore and Vector Loop, reveal that there are definitive results for 67 pairs of one-dimensional arrays that were tested.

• 대한전자공학회논문지
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• 제23권3호
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• pp.295-308
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• 1986

This paper presents a method of constructing multiple-valued logic functions based on Galois field. The proposed algorithm assigns all elements in GF(2**m) to bit codes that are easily converted binary. We have constructed an adder and a multiplier using a multiplexer after bit code operation (addition, multiplication) that is performed among elements on GF(2**m) obtained from the algorithm. In constructing a generalized multiple-valued logic functions, states are first minimized with a state-transition diagram, and then the circuits using PLA widely used in VLSI design for single and multiple input-output are realized.

• 대한전자공학회논문지
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• 제23권4호
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• pp.460-465
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• 1986

In this paper, a method for constructing of the sequential multiple-valued logic circuits over Galois field GF(px) is proposed. First, we derive the Talyor series over Galois field and the unique matrices which accords with the number of the element over the finite field, and we constdruct sequential multiple-valued logic circuits using these matrices. Computational procedure for traditional polynomial expansion can be reduced by using this method. Also, single and multi-input circuits can be easily implemented.

• 한국통신학회논문지
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• 제12권6호
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• pp.580-598
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• 1987

本 論文은 Galois Field를 利用하여 順序多値論理回路를 實現하는 하나의 방법을 제시하였다. 먼저 Taylor급수를 有限體上에서 成立하는 多項式에 對應하도록 전개시켜 多値組合論理回路의 固有行列을 산출하고 이 行列을 근거로 順序多値論理回路를 設計하였다. 本 論文은 組合回路를 構成하는 基本 개념을 順序論理回路에도 적용될 수 있도록 擴張한 것이다. 本 論文에서는 우선 組合論理回路의 構成理論을 擴張하여 單一入力 單一出力인 경우의 順序多値論理函數構成理論을 提示한 후 이를 擴張하여 單一入力 多出力인 경우의 順序多置論理函數構成理論을 提示하였다. 또한 이를 더욱 擴張하여 單一變數는 물론 多變數 多出力인 경우까지 提示하였다. 이때 多出力인 경우는 回路가 상호 獨立的이므로 Partition 개념에 의하여 처리하였다. 이 방법에 依하여 順序多値論理回路를 設計하면 종래의 多項式전개에 必要한 방대한 계산과정을 줄일 수 있었다. 또한 行列연산에 의하여 계산하므로 아무리 복잡한 論理函數라 하더라도 Computer Program처리가 가능하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.807-810
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• 1998

This paper propose the method to produce GRM(Generalized Reed-Muller)expansion. The general method to obtain GRM expansion coefficient for p valued n variable is derivation of single variable transform matrix and expand it n times using Kronecker product. In this case the size of matrix increases depending on the augmentation of variables. In this paper we propose the simple algorithm to produce GRM coefficient using a single variable transform matrix.

• 응용통계연구
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• 제33권1호
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• pp.61-74
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• 2020

심볼릭 자료 중 하나인 구간형 자료는 모든 관측값에서 단일 값이 아닌 구간을 값으로 취하며, 관측값 내에 변동이 존재한다는 특징을 갖는다. 주성분 분석은 자료의 분산을 최대로 설명하여 자료의 차원을 축소하는 방법이므로 구간형 자료의 주성분 분석은 관측값 간의 분산 뿐만 아니라 관측값 내의 분산 역시 설명하여야 한다. 본 논문에서는 구간형 자료의 세 가지 주성분 분석법을 소개하고자 한다. 또한 기존의 분위수 방법에서 균일분포를 사용하는 것이 아니라 구간의 중심점 부근이 좀 더 많은 정보를 가지고 있는 것으로 보고 절단정규분포를 사용하는 방법을 제안하였다. 모의실험과 OECD 관련 실제 통계 자료를 통하여 각 방법의 결과를 비교해 보았다. 마지막으로 분위수 방법의 경우 화살표 표현법을 통해 주성분 산점도를 그리고 분위수들의 위치와 분포를 확인하였다.

• East Asian mathematical journal
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• 제18권1호
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• pp.43-50
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• 2002

In this paper, we obtain some nonunique fixed point theorems of single valued and multivalued maps in metric and generalized metric spaces, one of which generalized the corresponding results of [5] and [6].

• 한국수학교육학회지시리즈B:순수및응용수학
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• 제5권1호
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• pp.23-32
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• 1998

In the present paper the author studies the decomposition property ($\delta$) of the bounded linear operators.

• Journal of Semiconductor Engineering
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• 제1권1호
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• pp.57-63
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• 2020

Complementary metal-oxide-semiconductor (CMOS) technology is now facing a power scaling limit to increase integration density. Since 1970s, multi-valued logic (MVL) has been considered as promising alternative to resolve power scaling challenge for increasing information density up to peta-scale level by reducing the system complexity. Over the past several decades, however, a power-scalable and mass-producible MVL technology has been absent so that MVL circuit and system implementation have been delayed. Recently, compact MVL device researches incorporating multiple-switching characteristics in a single device such as 2D heterojunction-based negative-differential resistance (NDR)/transconductance (NDT) devices and quantum-dot/superlattices-based constant intermediate current have been actively performed. Meanwhile, wafer-scale, energy-efficient and variation-tolerant ternary-CMOS (T-CMOS) technology has been demonstrated through commercial foundry. In this review paper, an overview for MVL development history including recent studies will be presented. Then, the status and its future research direction of MVL technology will be discussed focusing on the T-CMOS technology for peta-scale information processing in semiconductor chip.