• Journal of Welding and Joining
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• 제28권5호
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• pp.80-85
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• 2010

This study focused on laser assisted machining (LAM) of silicon nitride ceramic that efficiently removes the material through machining of the softened zone by local heating. The effects of laser-assisted machining parameters were studied for cost reduction, and active application in processing of silicon nitride ceramics in this study. Laser assisted machining of silicon nitride allows effective cutting using CBN tool by local heating of the cutting part to the softening temperature of YSiAlON using by the laser beam. When silicon nitride is sufficiently preheated, the surface is oxidized and decomposed and then forms bloating, micro crack and silicate layer, thereby making the cutting process more advantageous. HIPSN and SSN specimens were used to study the machining characteristics. Higher laser power makes severer oxidation and decomposition of both materials. Therefore, HIPSN and SSN specimens were machined more effectively at higher power.

• 한국추진공학회지
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• 제23권2호
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• pp.68-77
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• 2019

고체 및 액체 로켓 추진 기관 내열부품으로 사용하기 위하여 C/SiC 복합 재료를 LSI(Liquid Silicon Infiltration) 공법으로 개발하였다. 조성비에 따른 내열 특성은 아크 플라즈마, 초음속 토치 시험으로 평가하였으며 $H_2O$ 및 $CO_2$ 산화에 의한 유효 삭마식을 제시하였다. 연소시험을 통하여 고체 및 액체 추진기관용 노즐목 삽입재, 확대부 내열재 및 연소실 내열부품 등 다양한 형상으로 제작이 가능함을 확인하였으며 높은 내삭마 성능과 열구조 성능이 입증되었다.

• 한국결정성장학회지
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• 제9권6호
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• pp.597-600
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• 1999

단결정규소 웨이퍼를 15% HF-에탄올 용액에서 양극 산화시켜 다공질규소를 얻는 과정에서 전류밀도와 에칭시간에 따라 굴절률이 주기적으로 변하는 다층의 다공질규소층(porous silicon multilayers)을 구현하였다. 그리고 다층의 다공질규소층(I), 다공질규소 발광층, 또 다른 다층의 다공질규소층(II)의 순으로 구성된 porous silicon microcavity(PSM)를 제작하고 그 물성을 조사하였다. PSM 상하에 위치한 다층의 다공질규소층의 단면을 AFM(Atomic Force Microscope)으로 조사한 결과 고굴 절률과 저굴절률이 주기적으로 교차하는 층이 균일하게 형성되었으며, 중앙의 다공질규소 발광층도 균일하게 나타났다. 다층의 다공질규소층 및 다공질규소 발광층의 두께를 각각 실효파장의 1/4배 및 2배가 되도록 하였을 때 특정파장의 필터로 쓰일 수 있는 브래그 반사경(Bragg reflector)의 특성이 나타났다. 또한 PSM의 발광 스펙트럼은 그 반치폭이 현저히 감소하고 발광의 세기가 크게 증가되는 경향을 보였다.

• 한국윤활학회:학술대회논문집
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• 한국윤활학회 2002년도 제35회 춘계학술대회
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• pp.310-316
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• 2002

In this study, the effects of oxide layer formed on the wear tracks of TiN coated silicon wafer on friction and wear characteristics were investigated. Silicon wafer was used for the substrate of coated disk specimens, which were prepared by depositing TiN coating with $1{\mu}m$ in coating thickness. AISI 52100 steel ball was used for the counterpart. The tests were performed both in air for forming oxide layer on the wear track and in nitrogen to avoid oxidation. This paper reports characterization of the oxide layer effects on friction and wear characteristics using X-ray diffraction (XRD). Auger electron spectroscopy (AES), scanning electron microscopy (SEM) and sliding tests.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 추계학술대회 논문집 Vol.19
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• pp.7-8
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• 2006

The effects of heat treatment on the electrical properties of SGOI were examined. We proposed the optimized heat treatments for improving the interfacial electrical properties in SGOI-MOSFET. By applying the additional pre-RTA(rapid thermal annealing) before gate oxidation and post-RTA after dopant activation, the driving current, the transconductance, and the leakage current were improved significantly.

• 센서학회지
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• 제19권2호
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• pp.137-141
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• 2010

In this paper, we fabricated silicon piezoresistive pressure sensor with dry etching technology which used Deep-RIE and etching delay technology which used SOI(silicon-on-insulator) wafer. We improved pressure sensor offset and its temperature dependence by removing oxidation layer of SOI wafer which was used for dry etching delay layer. Sensitivity of the fabricated pressure sensor was about 0.56 mV/V${\cdot}$kPa at 10 kPa full-scale, and nonlinearity of the fabricated pressure sensor was less than 2 %F.S. The zero off-set change rate was less than 0.6 %F.S.

• 한국정밀공학회지
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• 제23권7호
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• pp.138-145
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• 2006

A nanopatterning technique was proposed and demonstrated for low cost and mass productive process using the scanning probe lithography (SPL) and soft lithography. The nanometer scale structure is fabricated by the localized generation of oxide patterning on the H-passivated (100) silicon wafer, and soft lithography was performed to replicate of nanometer scale structures. Both height and width of the silicon oxidation is linear with the applied voltagein SPL, but the growth of width is more sensitive than that of height. The structure below 100 nm was fabricated using HF treatment. To overcome the structure height limitation, aqueous KOH orientation-dependent etching was performed on the H-passivated (100) silicon wafer. Soft lithography is also performed for the master replication process. Elastomeric stamp is fabricated by the replica molding technique with ultrasonic vibration. We showed that the elastomeric stamp with the depth of 60 nm and the width of 428 nm was acquired using the original master by SPL process.

• 한국진공학회지
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• 제1권1호
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• pp.183-189
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• 1992

텅스텐 실리사이드를 축적전극으로 하는 얇은 N/O(SiO2/Si3N4) 구조막의 특성을 다 결성 실리콘의 경우와 비교 평가하였다. 누설전류 및 항복전압이 향상되었고 축적용량은 감 소하였다. 용량 감소의 원인중의 하나는 텅스텐 실리사이드 상의 산화막 성장률이 다결성 실리콘 위에서 보다 빠른 것이고 둘째는 열처리에 따라 다결정 실리콘 내 도판트 불순물이 텅스텐 실리사이드를 통하여 외향확산하여 다결정 실리콘 내에 공핍층을 형성하게 되고 공 핍층 용량으로 인하여 축적용량이 감소하게 된다.

• Carbon letters
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• 제8권2호
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• pp.91-94
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• 2007

The application of Carbon and graphite based materials in unprotected environment is limited to a temperature of $450^{\circ}C$ or so because of their susceptibility to oxidation at this temperature and higher. To over come these obstacles a low cost chemical vapour reaction process (CVR) was developed to give crystalline and high purity SiC coating on graphite and isotropic C/C composite. CVR is most effective carbothermal reduction method for conversation of a few micron of carbon layer to SiC. In the CVR method, a sic conversation layer is formed by reaction between carbon and gaseous reagent silicon monoxide at high temperature. Characterization of SiC coating was carried out using SEM. The other properties studied were hardness density and conversion efficiency.

• 한국세라믹학회지
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• 제36권8호
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• pp.863-870
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• 1999

SOI(silicon on insulafor) was fabricated through the direct bonding using (100) Si wafer and 4$^{\circ}$off (100) Si wafer to investigate the stacking faults in silicon at the Si/SiO2 oxidized and bonded interface. The treatment time of wafer surface using MSC-1 solution was varied in order to observe the effect of cleaning on bonding characteristics. As the MSC-1 treating time increased surface hydrophilicity was saturated and surface microroughness increased. A comparison of surface hydrophilicity and microroughness with MSC-1 treating time indicates that optimum surface modified condition for time was immersed in MSC-1 for 2 min. The SOI structure directly bonded using (100) Si wafer and 4$^{\circ}$off (100) Si wafer at the room temperature were annealed at 110$0^{\circ}C$ for 30 min. Then the stacking faults at the bonding and oxidation interface were examined after the debonding. The results show that there were anomalies in the gettering of the stacking faults at the bonded region.