• Journal of the Korean Solar Energy Society
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• v.31 no.4
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• pp.103-111
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• 2011

Laser drilling of vias is the one of key technologies in developing Emitter-Wrap Through(EWT) solar cell which is particularly attractive due to the use of industrial processing and common solar grade p-type silicon materials. While alternative economically feasible drilling process is not available to date, the processing time and laser induced damage should be as small as possible in this process. This paper provides an overview on various factors that should be considered in using the laser via drilling technology for developing highly efficient and industrially applicable EWT solar cells.

• Safety and Health at Work
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• v.12 no.3
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• pp.403-415
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• 2021

Background: This study aimed to assess the possibility of benzene exposure in workers of a Korean semiconductor manufacturing company by reviewing the issued patents. Methods: A systematic patent search was conducted with the Google "Advanced Patent Search" engine using the keywords "semiconductor" and "benzene" combined with all of the words accessed on January 24, 2016. Results: As a result of the search, we reviewed 75 patent documents filed by a Korean semiconductor manufacturing company from 1994 to 2010. From 22 patents, we found that benzene could have been used as one of the carbon sources in chemical vapor deposition for capacitor; as diamond-like carbon for solar cell, graphene formation, or etching for transition metal thin film; and as a solvent for dielectric film, silicon oxide layer, nanomaterials, photoresist, rise for immersion lithography, electrophotography, and quantum dot ink. Conclusion: Considering the date of patent filing, it is possible that workers in the chemical vapor deposition, immersion lithography, and graphene formation processes could be exposed to benzene from 1996 to 2010.

• Journal of Ceramic Processing Research
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• v.20 no.1
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• pp.48-53
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• 2019

Carbon fiber reinforced SiC composites (C/SiC) have high-temperature stability and excellent thermal shock resistance, and are currently being applied in extreme environments, for example, as aerospace propulsion parts or in high-performance brake systems. However, their low thermal conductivity, compared to metallic materials, are an obstacle to energy efficiency improvements via utilization of regenerative cooling systems. In order to solve this problem, the present study investigated the bonding strength between carbon fiber and matrix material within ceramic matrix composite (CMC) materials, demonstrating the relation between the microstructure and bonding, and showing that the mechanical properties and thermal conductivity may be improved by treatment of the carbon fibers. When fiber surface was treated with a nitric acid solution, the observed segment crack areas within the subsequently generated CMC increased from 6 to 10%; moreover, it was possible to enhance the thermal conductivity from 10.5 to 14 W/m·K, via the same approach. However, fiber surface treatment tends to cause mechanical damage of the final composite material by fiber etching.

• Korean Journal of Materials Research
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• v.34 no.2
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• pp.105-110
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• 2024

Scanning probe microscopy (SPM) has become an indispensable tool in efforts to develop the next generation of nanoelectronic devices, given its achievable nanometer spatial resolution and highly versatile ability to measure a variety of properties. Recently a new scanning probe microscope was developed to overcome the tip degradation problem of the classic SPM. The main advantage of this new method, called Reverse tip sample (RTS) SPM, is that a single tip can be replaced by a chip containing hundreds to thousands of tips. Generally for use in RTS SPM, pyramid-shaped diamond tips are made by molding on a silicon substrate. Combining RTS SPM with Scanning spreading resistance microscopy (SSRM) using the diamond tip offers the potential to perform 3D profiling of semiconductor materials. However, damage frequently occurs to the completed tips because of the complex manufacturing process. In this work, we design, fabricate, and evaluate an RTS tip chip prototype to simplify the complex manufacturing process, prevent tip damage, and shorten manufacturing time.

• Applied Chemistry for Engineering
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• v.26 no.5
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• pp.543-548
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• 2015

Si/C/CNF composites as anode materials for lithium-ion batteries were examined to improve the capacity and cycle performance. Si/C/CNF composites were prepared by the fabrication process including the synthesis and magnesiothermic reduction of SBA-15 to obtain Si/MgO by ball milling and the carbonization of phenol resin with CNF and HCl etching. Prepared Si/C/CNF composites were then analysed by BET, XRD, FE-SEM and TGA. Among SBA-15 samples synthesized at reaction temperatures between 50 and $70^{\circ}C$, the SBA-15 at $60^{\circ}C$ showed the largest specific surface area. Also the electrochemical performances of Si/C/CNF composites as an anode electrode were investigated by constant current charge/discharge test, cyclic voltammetry and impedance tests in the electrolyte of LiPF6 dissolved in mixed organic solvents (EC : DMC : EMC = 1 : 1 : 1 vol%). The coin cell using Si/C/CNF composites (Si : CNF = 97 : 3 in weight) showed better capacity (1,947 mAh/g) than that of other composition coin cells. The capacity retention ratio decreased from 84% (Si : CNF = 97 : 3 in weight) to 77% (Si : CNF = 89 : 11 in weight). It was found that the Si/C/CNF composite electrode shows an improved cycling performance and electric conductivity.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.1-5
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• 2006

We prepared 80 nm-thick TiSix on each 70 nm-thick amorphous silicon and polysilicon substrate using an RF sputtering with $TiSi_2$ target. TiSix composite silicide layers were stabilized by rapid thermal annealing(RTA) of $800^{\circ}C$ for 20 seconds. Line width of $0.5{\mu}m$ patterns were embodied by photolithography and dry etching process, then each additional annealing process at $750^{\circ}C\;and\;850^{\circ}C$ for 3 hours was executed. We investigated the change of sheet resistance with a four-point probe, and cross sectional microstructure with a field emission scanning electron microscope(FE-SEM) and transmission electron microscope(TEM), respectively. We observe an abrupt change of resistivity and voids at the silicide surface due to interdiffusion of silicide and composite titanium silicide in the amorphous substrates with additional $850^{\circ}C$ annealing. Our result implies that the electrical resistance of composite titanium silicide may be tunned by employing appropriate substrates and annealing condition.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.55-59
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• 2018

In this paper, we investigated the characteristics of shear stress type piezoresistor on a diaphragm structure formed by MEMS (Microelectromechanical System) technology of silicon-direct-bonding (SDB) wafers with Si/$SiO_2$/Si-sub. The diaphragm structure formed by etching the backside of the wafer using a TMAH aqueous solution can be used for manufacturing various sensors. In this study, the optimum shape condition of the shear stress type piezoresistor formed on the diaphragm is found through ANSYS simulation, and the diaphragm structure is formed by using the semiconductor microfabrication technique and the shear stress formed by boron implantation. The characteristics of the piezoelectric resistance are compared with the simulation results. The sensing diaphragm was made in the shape of an exact square. It has been experimentally found that the maximum shear stress for the same pressure at the center of the edge of the diaphragm is generated when the structure is in the exact square shape. Thus, the sensing part of the sensor has been designed to be placed at the center of the edge of the diaphragm. The prepared shear stress type piezoresistor was in good agreement with the simulation results, and the sensitivity of the piezoresistor formed on the $2200{\mu}m{\times}2200{\mu}m$ diaphragm was $183.7{\mu}V/kPa$ and the linearity of 1.3 %FS at the pressure range of 0~100 kPa and the symmetry of sensitivity was also excellent.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.2 s.43
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• pp.17-21
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• 2007

Dense and periodic arrays of holes and Si nano dots were fabricated on silicon substrate. The nanopatterned holes were approximately $15{\sim}40nm$ wide, 40 nm deep and $40{\sim}80\;nm$ apart. To obtain nano-size patterns, self?assembling diblock copolymer were used to produce layer of hexagonaly ordered parallel cylinders of polymethylmethacrylate (PMMA) in polystyrene(PS) matrix. The PMMA cylinders were degraded and removed with acetic acid rinse to produce a PS. $100\;{\AA}-thick$ Au thin film was deposited by using e-beam evaporator. PS template was removed by lift-off process. Arrays of Au nano dots were transferred by using Fluorine-based reactive ion etching(RE). Au nano dots were removed by sulfuric acid. Si nano dots size and height were $30{\sim}70\;nm$ and $10{\sim}20\;nm$ respectively.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.3
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• pp.67-71
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• 2014

An attempt to grow high quality GaN on silicon substrate using metal organic chemical vapor deposition (MOCVD), herein GaN epitaxial layers were grown on various Si(111) substrates. Thin Platinum layer was deposited on Si(111) substrate using sputtering, followed by thermal annealing to form Pt nano-clusters which act as masking layer during dry-etched with inductively coupled plasma-reactive ion etching to generate nano-patterned Si(111) substrate. In addition, micro-patterned Si(111) substrate with circle shape was also fabricated by using conventional photo-lithography technique. GaN epitaxial layers were subsequently grown on micro-, nano-patterned and conventional Si (111) substrate under identical growth conditions for comparison. The GaN layer grown on nano-patterned Si (111) substrate shows the lowest crack density with mirror-like surface morphology. The FWHM values of XRD rocking curve measured from symmetry (002) and asymmetry (102) planes are 576 arcsec and 828 arcsec, respectively. To corroborate an enhancement of the growth quality, the FWHM value achieved from the photoluminescence spectra also shows the lowest value (46.5 meV) as compare to other grown samples.

• Journal of IKEEE
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• v.20 no.3
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• pp.220-225
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• 2016

In this paer, low on-resistance and high-power trench gate MOSFET (Metal-Oxide-Silicon Field Effect Transistor) incorporating current sensing FET (Field Effect Transistor) is proposed and evaluated. The trench gate power MOSFET was fabricated with $0.6{\mu}m$ trench width and $3.0{\mu}m$ cell pitch. Compared with the main switching MOSFET, the on-chip current sensing FET has the same device structure and geometry. In order to improve cell density and device reliability, self-aligned trench etching and hydrogen annealing techniques were performed. Moreover, maintaining low threshold voltage and simultaneously improving gate oxide relialility, the stacked gate oxide structure combining thermal and CVD (chemical vapor deposition) oxides was adopted. The on-resistance and breakdown voltage of the high density trench gate device were evaluated $24m{\Omega}$ and 100 V, respectively. The measured current sensing ratio and it's variation depending on the gate voltage were approximately 70:1 and less than 5.6 %.