• Transactions of the Society of Information Storage Systems
• /
• v.1 no.2
• /
• pp.182-187
• /
• 2005

A large area micro mirror is an optical element that functions as changing an optical path by reflection in integrated optical system. We fabricated the large area silicon mirror by anisotropic etching using MEMS for implementation of integrated optical pickup. In this work, we report the optimum conditions to better fabricate and design, greatly improve mirror surface quality. To obtain mirror surface of $45^{\circ},\;9.74^{\circ}$ off-axis silicon wafer from (100) plane was used in etching condition of $80^{\circ}C$ with 40wt.% KOH solution. After wet etching, polishing process by MR fluid was applied to mirror surface for reduction of roughness. In the next step, after polymer coating on the polished Si wafer, the Si mirror was fabricated by UV curing using a trapezoid bar-type way structure. Finally, we obtained peak to valley roughness about 50 nm in large area of $mm^2$ and it is applicable to optical pickup using blu-ray wavelength as well as infrared wavelength.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.29 no.8
• /
• pp.455-460
• /
• 2016

A textured front surface is required in high efficiency silicon solar cells to reduce reflectance and to improve light trapping. Wet etching with alkaline solution is usually applied for mono crystalline silicon solar cells. However, alkali texturing method is not appropriate for multi-crystalline silicon wafers due to grain boundary of random crystallographic orientation. Accordingly, acid texturing method is generally used for multi-crystalline silicon wafers to reduce the surface reflectance. To reduce reflectivity of multi-crystalline silicon wafers, double texturing method with combination of acid and reactive ion etching is an attractive technical solution. In this paper, we have studied to optimize RIE condition by different RF power condition (100, 150, 200, 250, 300 W).

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 1996.11a
• /
• pp.725-730
• /
• 1996

The key process in silicon surface micromachining is the selective etching of a sacrificial layer to release the silicon microstructure. The newly developed anhydrous HF/$CH_3$OH gas phase etching of TEOS (teraethylorthosilicate) sacrificial layers onto the polysilicon and the nitride substrates was employed to release the polysilicon microstructures. A residual product after TEOS etching onto the nitride substrate was observed on the surface, since a SiOxNy layer is formed on the TEOS/nitride interface. The polysilicon microstructures are stuck to the underlying substrate because SiOxNy layer does not vaporize. We found that the only sacrificial etching without any residual product and stiction is TEOS etching onto the polysilicon substrate.

• Proceedings of the KIEE Conference
• /
• 1992.07b
• /
• pp.850-853
• /
• 1992

A cryogenic electron cyclotron resonance plasma etching system has been built to study wafer-temperature in the silicon etching characteristics. The wafer temperature was controlled from -150 to +30 $^{\circ}C$ during etching using the liquid nitrogen cooled helium gas. Although silicon was etched isotropically in $SF_6$ plasma at room temperatures, we found that it is possible to suppress the etch undercut in Si by reducing a substrate temperature without side wall passivation. In addition, the selectivity of silicon to photoresist was improved considerably at a low wafer temperature. Etch rates, anisotropy and selectivity to photo resist are measured as a function of the wafer temperature in the region of -125 $\sim$ 25$^{\circ}C$ and rf bias power of 20W $\sim$ 80W.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.08a
• /
• pp.278-278
• /
• 2011

수소 중성입자빔을 이용한 silicon etching은 기존의 silicon etching 공정 가스(Fluorine이나 Chlorine 계열의 가스) 사용 시 배출되는 유해 가스로 인한 지구 온난화 방지 및 폐기물 처리에 추가적인 비용이 발생하지 않는 친환경 etching 공정이다. 본 연구에 사용된 수소 중성입자빔을 발생시키기 위한 플라즈마 소스는 낮은 압력에서 높은 플라즈마 밀도를 발생시킬 수 있는 ECR 플라즈마 소스를 사용하였으며 중성입자빔의 에너지를 조절할 수 있는 중성화판과 플라즈마로부터의 전하손상을 방지할 수 있어 charge free 공정을 가능하게 하는 Limiter로 구성되어 있다. 본 연구에서는 플라즈마 밀도, 공정 압력 그리고, 중성입자빔의 에너지를 조절하여 수소 중성입자빔을 이용한 poly-crystal silicon과 a-Si:H 간의 etch rate와 etching selectivity를 관찰하였다.

• Korean Journal of Materials Research
• /
• v.16 no.4
• /
• pp.213-217
• /
• 2006

In this study, atomic layer etching of Si has been carried out using $Cl_2$ adsorption followed by the irradiation Ar neutral beam of low energy. In this experiment, the etch rate of Si was dependent on the $Cl_2$ pressure(the surface coverage of chlorine) and the irradiation time of Ar neutral beam(the flux density of Ar neural beam). And the etch rate of Si(100) and Si(111) were saturated exactly at one monolayer per cycle with $1.36{\AA}/cycle\;and\;1.57{\AA}/cycle$, respectively.

• Current Photovoltaic Research
• /
• v.5 no.4
• /
• pp.105-108
• /
• 2017

The reactive ion etching (RIE) technology which enables nano-texturatization of surface is applied on monocrystalline silicon solar cell. The additional RIE process on alkalized textured surface further improves the blue response and short circuit current. Such parameter is characterized by surface reflectance and quantum efficiency measurement. By varying the RIE process time and matching the subsequent processes, the absolute efficiency gain of 0.13% is achieved. However, the result indicates potential efficiency gain could be higher due to process integration. The critical etch process time is discussed which minimizes both front surface reflectance and etching damage, considering the challenges of required system throughput in industry.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1998.06a
• /
• pp.411-414
• /
• 1998

In this paper, the silicon-nitride membrane structure for IR sensor was fabricated through the etching and the direct bonding. The PT layer as a IR detection layer was deposited on the membrane and its characteristics were measured. The attack of PT layer during the etching of silicon wafer as well as the thermal isolation of the IR detection layer can be solved through the method of bonding/etching of silicon wafer. Because the PT layer of c-axial orientation rained thermal polarization without polling, the more integration capability can be achieved. The surface roughness of the membrane was measured by AFM, the micro voids and the non-contacted area were inspected by IR detector, and the bonding interface was observed by SEM. The polarization characteristics and the dielectric characteristics of the PT layer were measured, too.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.11 no.10
• /
• pp.815-819
• /
• 1998

The silicon-nirtide membrane structure for IR sensor was fabricated through the etching and the direct bonding. The PRO($PbTiO_3$ ) layer for a IR detection was coated on the membrane and its characteristics were measured. The a attack of PTO layer during the etching of silicon wafer as well as the thermal isolation of the IR detection layer were eliminated through the method of bonding/etching of silicon wafer. The surface roughness of the membrane was measured by AFM, the micro voids and the non-contacted area were inspected by the PTO layer were measured, too.

• Journal of the Korean Society for Precision Engineering
• /
• v.21 no.5
• /
• pp.24-31
• /
• 2004

Masking effect of the nanoscratched silicon (100) surface was studied and applied to a maskless nanofabrication technique. First, the surface of the silicon (100) was machined by ductile-regime nanomachining process using the scratch option of the Nanoindenter${ \circledR}$ XP. To clarify the possibility of the nanoscratched silicon surfaces for the application to wet etching mask, the etching characteristic with a KOH solution was evaluated at room temperature. After the etching process, the convex nanostructures were made due to the masking effect of the mechanically affected layer. Moreover, the height and the width of convex structures were controlled with varying normal loads during nanoscratch.