• Transactions of the Korean Society of Mechanical Engineers B
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• v.30 no.5 s.248
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• pp.405-412
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• 2006

In order to realize a stably propagating flame in a narrow channel, flame instabilities resulting from flame-wall interaction should be avoided. In particular flame quenching is a significant issue in micro combustion devices; quenching is caused either by excessive heat loss or by active radical adsorptions at the wall. In this paper, the relative significance of thermal and chemical effects on flame quenching is examined by means of quenching distance measurement. Emphasis is placed on the effects of surface defect density on flame quenching. To investigate chemical quenching phenomenon, thermally grown silicon oxide plates with well-defined defect distribution were prepared. ion implantation technique was used to control defect density, i.e. the number of oxygen vacancies. It has been found that when the surface temperature is under $300^{\circ}C$, the quenching distance is decreased on account of reduced heat loss; as the surface temperature is increased over $300^{\circ}C$, however, quenching distance is increased despite reduced heat loss effect. Such abberant behavior is caused by heterogeneous surface reactions between active radicals and surface defects. The higher defect density, the larger quenching distance. This result means that chemical quenching is governed by radical adsorption that can be parameterized by oxygen vacancy density on the surface.

• Korean Journal of Metals and Materials
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• v.50 no.2
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• pp.152-158
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• 2012

The effect of current waveform on Cu filling into TSV (through-silicon via) and the bottom-up ratio of Cu were investigated for three dimensional (3D) Si chip stacking. The TSV was prepared on an Si wafer by DRIE (deep reactive ion etching); and its diameter and depth were 30 and $60{\mu}m$, respectively. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. The current waveform was varied like a pulse, PPR (periodic pulse reverse) and 3-step PPR. As experimental results, the bottom-up ratio by the pulsed current decreased with increasing current density, and showed a value of 0.38 on average. The bottom-up ratio by the PPR current showed a value of 1.4 at a current density of $-5.85mA/cm^2$, and a value of 0.91 on average. The bottom-up ratio by the 3-step PPR current increased from 1.73 to 5.88 with time. The Cu filling by the 3-step PPR demonstrated a typical bottom-up filling, and gave a sound filling in a short time.

• Journal of the Korean Society for Heat Treatment
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• v.34 no.5
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• pp.239-244
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• 2021

Following Silicon Carbide, single crystal diamond continues to attract attention as a next-generation semiconductor substrate material. In addition to excellent physical properties, large area and productivity are very important for semiconductor substrate materials. Research on the increase in area and productivity of single crystal diamonds has been carried out using various devices such as HPHT (High Pressure High Temperature) and MPECVD (Microwave Plasma Enhanced Chemical Vapor Deposition). We hit the limits of growth rate and internal defects. However, HFCVD (Hot Filament Chemical Vapor Deposition) can be replaced due to the previous problem. In this study, HFCVD confirmed the distance between the substrate and the filament, the accompanying growth rate, the surface shape, and the Raman shift of the substrate after vapor deposition according to the vapor deposition temperature change. As a result, it was confirmed that the difference in the growth rate of the single crystal substrate due to the change in the vapor deposition temperature was gained up to 5 times, and that as the vapor deposition temperature increased, a large amount of polycrystalline diamond tended to be generated on the surface.

• Korean Journal of Metals and Materials
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• v.49 no.5
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

• Journal of Adhesion and Interface
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• v.24 no.2
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• pp.60-63
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• 2023

The AlGaN/GaN heterostructure has high electron mobility due to the two-dimensional electron gas (2-DEG) layer, and has the characteristic of high breakdown voltage at high temperature due to its wide bandgap, making it a promising candidate for high-power and high-frequency electronic devices. Despite these advantages, there are factors that affect the reliability of various device properties such as current collapse. To address this issue, this paper used metal-organic chemical vapor deposition to continuously deposit AlGaN/GaN heterostructure and SiN passivation layer. Material and electrical properties of GaN HEMTs with/without SiN cap layer were analyzed, and based on the results, low-frequency noise characteristics of GaN HEMTs were measured to analyze the conduction mechanism model and the cause of defects within the channel.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.124-130
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• 2023

Recently, fan out wafer level packaging, which enables high integration, miniaturization, and low cost, is being rapidly applied in the semiconductor industry. In particular, FOWLP is attracting attention in the mobile and Internet of Things fields, and is recognized as a core technology that will lead to technological advancements such as 5G, self-driving cars, and artificial intelligence in the future. However, as chip density and package size within the package increase, FOWLP warpage is emerging as a major problem. These problems have a direct impact on the reliability and electrical performance of semiconductor products, and in particular, cause defects such as vacuum leakage in the manufacturing process or lack of focus in the photolithography process, so technical demands for solving them are increasing. In this paper, warpage simulation according to the thickness of FOWLP material was performed using finite element analysis. The thickness range was based on the history of similar packages, and as a factor causing warpage, the curing temperature of the materials undergoing the curing process was applied and the difference in deformation due to the difference in thermal expansion coefficient between materials was used. At this time, the stacking order was reflected to reproduce warpage behavior similar to reality. After performing finite element analysis, the influence of each variable on causing warpage was defined, and based on this, it was confirmed that warpage was controlled as intended through design modifications.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.34 no.2
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• pp.41-47
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• 2024

In this study, the resistance characteristics of semi-insulating SiC single crystals grown using the PVT method were investigated, considering the purity level of SiC source powders used in PVT growth and the cooling procedure after crystal growth. Two β-SiC powders with different purities were employed, and the cooling rate after growth was adjusted to achieve various resistance values. 4-inch HPSI-SiC ingots were grown using the PVT method, utilizing SiC powders with low nitrogen concentration and relatively high nitrogen concentration. These ingots were then subjected to different cooling procedures to modify the cooling rate. Transmission/absorption spectra and crystal quality of the grown crystals were analyzed through UV/VIs/NIR spectroscopy and X-ray rocking curve analysis, respectively. Additionally, electrical properties were investigated through non-contact resistivity analysis to identify the dominant factors influencing resistivity properties.

• Korean Journal of Materials Research
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• v.11 no.7
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• pp.556-561
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• 2001

We prepared a new a SOS(silicon-on-silicide) wafer pair which is consisted of Si(100)/1000$\AA$-NiSi Si (100) layers. SOS can be employed in MEMS(micro- electronic-mechanical system) application due to low resistance of the NiSi layer. A thermally evaporated $1000\AA$-thick Ni/Si wafer and a clean Si wafer were pre-mated in the class 100 clean room, then annealed at $300~900^{\circ}C$ for 15hrs to induce silicidation reaction. SOS wafer pairs were investigated by a IR camera to measure bonded area and probed by a SEM(scanning electron microscope) and TEM(transmission electron microscope) to observe cross-sectional view of Si/NiSi. IR camera observation showed that the annealed SOS wafer pairs have over 52% bonded area in all temperature region except silicidation phase transition temperature. By probing cross-sectional view with SEM of magnification of 30,000, we found that $1000\AA$-thick uniform NiSi layer was formed at the center area of bonded wafers without void defects. However we observed debonded area at the edge area of wafers. Through TEM observation, we found that $10-20\AA$ thick amourphous layer formed between Si surface and NiSix near the counter part of SOS. This layer may be an oxide layer and lead to degradation of bonding. At the edge area of wafers, that amorphous layer was formed even to thickness of $1500\AA$ during annealing. Therefore, to increase bonding area of Si NiSi ∥ Si wafer pairs, we may lessen the amorphous layers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.11
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• pp.771-780
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• 2001

It is indispensable to use the process and device simulation tool in order to analyze accurately the electrical characteristics of ULSI CMOS devices, in addition to developing and manufacturing those devices. The 3D Monte Carlo (MC) simulation result is not efficient for large-area application because of the lack of simulation particles. In this paper is reported a new efficient simulation strategy for 3D MC ion implantation into large-area application using the 3D MC code of TRICSI(TRansport Ions into Crystal Silicon). The strategy is related to our newly proposed split-trajectory method and ion-splitting method(ion-shadowing approach) for 3D large-area application in order to increase the simulation ions, not to sacrifice the simulation accuracy for defects and implanted ions. In addition to our proposed methods, we have developed the cell based 3D interpolation algorithm to feed the 3D MC simulation result into the device simulator and not to diverge the solution of continuous diffusion equations for diffusion and RTA(rapid thermal annealing) after ion implantation. We found that our proposed simulation strategy is very computationally efficient. The increased number of simulation ions is about more than 10 times and the increase of simulation time is not twice compared to the split-trajectory method only.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.11 no.5
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• pp.224-230
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• 2001

The characteristics of $NO/N_2O$ annealed reoxidized nitrided oxide being studied as super thin gate oxide and gate dielectric layers of Non-Volatile Semiconductor Memory (NVSM) were investigated by Dynamic Secondary Ion Mass Spectrometry (D-SIMS), Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS), and Auger Electron Spectroscopy (AES). The specimen was annealed by $NO/N_2O$ after initial oxide process and then rcoxidized for nitrogen redistribution in nitrided oxide. Out-diffusion of incorporated nitrogen during the wet oxidation in reoxidation process took place more strongly than that of the dry oxidation. It seems to indicate that hydrogen plays a role in breaking the Si N bonds. As reoxidation proceeds, incorporated nitrogen of $NO/N_2O$ annealed nitrided oxide is obsen-ed to diffuse toward the surface and substrate at the same time. ToF-SIMS results show that SiON species are detected at the initialoxide interface, and Si,NO species near the new $Si_2NO$ interface that formed after reoxidation. These SiON and $Si_2NO$ species most likely to relate to the origin of the state of memory charge traps in reoxidized nitrided oxide, because nitrogen dangling bonds of SiON and silicon dangling bonds of $Si_2NO$ are contained defects associated with memory effect.