Korean Journal of Metals and Materials (대한금속재료학회지)

The Korean Institute of Metals and Materials (대한금속재료학회)
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High Speed Cu Filling into Tapered TSV for 3-dimensional Si Chip Stacking

3차원 Si칩 실장을 위한 경사벽 TSV의 Cu 고속 충전

  • Kim, In Rak (Dept. of Materials Sci. and Eng., University of Seoul) ;
  • Hong, Sung Chul (Dept. of Materials Sci. and Eng., University of Seoul) ;
  • Jung, Jae Pil (Dept. of Materials Sci. and Eng., University of Seoul)
  • 김인락 (서울시립대학교 신소재공학과) ;
  • 홍성철 (서울시립대학교 신소재공학과) ;
  • 정재필 (서울시립대학교 신소재공학과)
  • Received : 2010.12.23
  • Published : 2011.05.25
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Abstract

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

Keywords

Acknowledgement

Supported by : 서울

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