• Journal of the Korean Ceramic Society
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• v.38 no.10
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• pp.871-875
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• 2001

Cobalt silicidation at sidewall spacer edge of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with post annealing treatment for capacitor forming process has been investigated as a function of dopant species. Cobalt silicidation of nMOSFET with n-type Lightly Doped Drain (LDD) and pMOSFET with p-type LDD produces a well-developed cobalt silicide with its lateral growth underneath the sidewall spacer. In case of pMOSFET with n-type LDD, however, a void is formed at the sidewall spacer edge with no lateral growth of cobalt silicide. The void formation seems to be due to a retarded silicidation process at the LDD region during the first Rapid Thermal Annealing (RTA) for the reaction of Co with Si, resulting in cobalt mono silicide at the LDD region. The subsequent second RTA converts the cobalt monosilicide into cobalt disilicide with the consumption of Si atoms from the Si substrate, producing the void at the sidewall spacer edge in the Si region. The void formed at the sidewall spacer edge serves as a resistance in the current-voltage characteristics of the pMOSFET device.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.3-4
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• 2006

In this paper, a nickel silicide technology with post-silicidation annealing effect for thin film SOI devices is investigated in detail. Although lower resistivity Ni silicide can be easily obtained at low forming temperature, poor thermal stability and changing of characteristic are serious problems during the post silicidation annealing like ILD (Inter Layer Dielectric) deposition or metallization. So these effects are observed as deposited Ni thickness differently on As doped SOI (Si film 30nm). Especially, the sheet resistance of Ni thickness deposited 20nm was lower than 30nm before the post silicidation annealing. But after the post silicidation annealing, the sheet resistance was changed. Therefore, in thin film SOI MOSFETs or Ni-FUSI technology that the Si film is less than 50nm, it is important to decide the thickness of deposited Ni in order to avoid forming high resistivity silicide.

• Journal of the Korean Ceramic Society
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• v.36 no.6
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• pp.604-610
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• 1999

Silicide layer structures and morphology degradation of the surface and interface of the silicide layers for he Co/refractory metal bilayer sputter-deposited on the P-doped polycrystalline Si substrate and subjected to rapid thermal annealing were investigated and compared with those on the single Si substrate. The CoSi-CoSi2 phase transition temperature is lower an morphology degradation of the silcide layer occurs more severely for the Co/refractorymetal bilayer on the P-doped polycrystalline Si substrate than on the single Si substrate. Also the final layer structure and the morphology of the films after silicidation annealing was found to depend strongly upon the interlayer metal. The layer structure after silicidation annealing of Co/Hf/doped-poly Si is Co-Hf alloy/polycrystalline CoSi2/poly Si substrate while that of Co/Nb is polycrystalline CoSi2/NbSi2/polycrystalline CoSi2/poly Si.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.195-196
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• 2005

In recent years, as the needs of MOS's a high quality is desired to get the superior electrical characteristics and reliability on MOSFET. As an alternative gate dielectric have drawn considerable alternation due to their superior performance and reliability properties over MOSFET, 2'nd silicidation formation process has been proposed as a dielectric growth/annealing process. In this study the author observed process characteristics on MOS structure. In view points of the process characteristics of MOS capacitor, the oxygen & polysilicon was analyzed by SIMS analysis on l'st & 2'nd Ti process, the oxygen and Si2 contents[Count/sec] of 1.5e3 & 3.75e4 on l'st process and l.1e3 & 2.94e4 on 2'nd process, the Ti contents' of 8.2e18 & 6.5e18 on 1'st and 2'nd process. The sheet resistance[$\Omega/sq.$] was 4.5 & 4.0, the film stress[dyne/cm 2] of 1.09e10 & 1.075e10 on l'st and 2'nd process. I could achieved the superior MOS characteristics by 2'nd silicidation process.

• Korean Journal of Materials Research
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• v.12 no.11
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• pp.883-888
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• 2002

We investigated the void formation in composite-titanium silicide($TiSi_2$) process. We varied the process conditions of polycrystalline/amorphous silicon substrate, composite $TiSi_2$ deposition temperature, and silicidation annealing temperature. We report that the main reason for void formation is the mass transport flux discrepancy of amorphous silicon substrate and titanium in composite layer. Sheet resistance in composite $TiSi_2$ without patterns is mainly affected by silicidation rapid thermal annealing (RTA) temperature. In addition, sheet resistance does not depend on the void defect density. Sheet resistance with sub-0.5 $\mu\textrm{m}$ patterns increase abnormally above $850^{\circ}C$ due to agglomeration. Our results imply that $sub-750^{\circ}C$ annealing is appropriate for sub 0.5 $\mu\textrm{m}$ composite X$sub-750_2$ process.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.6
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• pp.51-58
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• 1995

Major limiting factors in the linear scaling down of the shallow source/drain junction are the boron channeling effect and the Si cosumption phenomenon during silicidation. We can solve these problems by As preamorphization of the predeposited amorphous Si layer. The predeposited amorphous Si layer made the junction depth decrease to nearly the thickness value of the layer and was effectively utilized as the cosumed Si source during Ti silicidation. This method was applied to the actual fabrication of PMOSFET through SES (selectricely etched Si) techology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.11a
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• pp.130-131
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• 2005

In the era of submicron devices, super ultra thin gate oxide characteristics are required. Titanium silicide process has studied gate oxide reliability and dielectric strength characteristics as the composition of gate electrode. In this study the author observed process characteristics on MOS structure. In view point of the process characteristics of MOS capacitor, the oxygen & Ti, Si2 was analyzed by SIMS analysis on before and after annealing with 1,2 step silicidation, the Ti contents[Count/sec]of $9.5{\times}1018$ & $6.5{\times}1018$ on before and after 2'nd anneal. The oxygen contents[Count/sec] of $4.3{\times}104$ & $3.65{\times}104$, the Si contents[Count/sec] of $4.2{\times}104$ & $3.7{\times}104$ on before and after 2'nd anneal. The rms value[A] was 4.98, & 4.03 on before and after 2'nd anneal.

• Journal of the Korean Ceramic Society
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• v.33 no.9
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• pp.1012-1018
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• 1996

To investigate the final structures and reactions of silicides a somewhat thick Ti monolayer Co monolayer and Co/Ti bilayer films were deposited on single Si(100) wafer by electron beam evaporation followed by heat treatment using RTA system in N2 ambient. TiO2 film formed between Ti and TiSi2 layers due to oxgen or moisture in the Ti monolayer sample. The final layer structure obtained after the silicidation heat-treatment of the Co/Ti bilayer sample turned out to be TiSi2/CoSi2/Ti-Co-Si alloy/CoSi2/Si sbustrate. This implies that imperfect layer inversion occurred due to the formation of Ti-Co-Si intermediate phase.

• Proceedings of the Materials Research Society of Korea Conference
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• 1995.11a
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• pp.8-8
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• 1995

• Proceedings of the Materials Research Society of Korea Conference
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• 2000.11a
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• pp.96-96
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• 2000