• Title/Summary/Keyword: signal control scheme

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Error Resilient Video Coding Techniques Using Multiple Description Scheme (다중 표현을 이용한 에러에 강인한 동영상 부호화 방법)

  • 김일구;조남익
    • Journal of Broadcast Engineering
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    • v.9 no.1
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    • pp.17-31
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    • 2004
  • This paper proposes an algorithm for the robust transmission of video in error Prone environment using multiple description codingby optimal split of DCT coefficients and rate-distortionoptimization framework. In MDC, a source signal is split Into several coded streams, which is called descriptions, and each description is transmitted to the decoder through different channel. Between descriptions, structured correlations are introduced at the encoder, and the decoder exploits this correlation to reconstruct the original signal even if some descriptions are missing. It has been shown that the MDC is more resilient than the singe description coding(SDC) against severe packet loss ratecondition. But the excessive redundancy in MDC, i.e., the correlation between the descriptions, degrades the RD performance under low PLR condition. To overcome this Problem of MDC, we propose a hybrid MDC method that controls the SDC/MDC switching according to channel condition. For example, the SDC is used for coding efficiency at low PLR condition and the MDC is used for the error resilience at high PLR condition. To control the SDC/MDC switching in the optimal way, RD optimization framework are used. Lagrange optimization technique minimizes the RD-based cost function, D+M, where R is the actually coded bit rate and D is the estimated distortion. The recursive optimal pet-pixel estimatetechnique is adopted to estimate accurate the decoder distortion. Experimental results show that the proposed optimal split of DCT coefficients and SD/MD switching algorithm is more effective than the conventional MU algorithms in low PLR conditions as well as In high PLR condition.

DRAM Package Substrate Using Aluminum Anodization (알루미늄 양극산화를 사용한 DRAM 패키지 기판)

  • Kim, Moon-Jung
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.4
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    • pp.69-74
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    • 2010
  • A new package substrate for dynamic random access memory(DRAM) devices has been developed using selective aluminum anodization. Unlike the conventional substrate structure commonly made by laminating epoxy-based core and copper clad, this substrate consists of bottom aluminum, middle anodic aluminum oxide and top copper. Anodization process on the aluminum substrate provides thick aluminum oxide used as a dielectric layer in the package substrate. Placing copper traces on the anodic aluminum oxide layer, the resulting two-layer metal structure is completed in the package substrate. Selective anodization process makes it possible to construct a fully filled via structure. Also, putting vias directly in the bonding pads and the ball pads in the substrate design, via in pad structure is applied in this work. These arrangement of via in pad and two-layer metal structure make routing easier and thus provide more design flexibility. In a substrate design, all signal lines are routed based on the transmission line scheme of finite-width coplanar waveguide or microstrip with a characteristic impedance of about $50{\Omega}$ for better signal transmission. The property and performance of anodic alumina based package substrate such as layer structure, design method, fabrication process and measurement characteristics are investigated in detail.

Optical security system using multi-phase separation and phase-wrapping method (다중 위상 분할과 위상 랩핑 방법을 이용한 광 암호화 시스템)

  • Shin Chang Mok;Kim Soo Joong;Seo Dong Hoan
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.6 s.336
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    • pp.31-38
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    • 2005
  • In this paper, we proposed an optical security system based on a gray-image exclusive-OR encryption using multi-phase separation and phase-wrapping method. For encryption, a gray image is sliced into binary images, which have the same pixel value, and these images are encrypted by modified XOR rules with binary random images. The XORed images and the binary images respectively combined and converted into full phase images, called an encrypted image and a key image. For decryption, when the encrypted image and key image are used as inputs on optical elements, Practically due to limited controllability of phase range in optical elements, the original gray image cannot be efficiently reconstructed by these optical elements. Therefore, by decreasing the phase ranges of the encrypted image and key image using a phase-wrapping method and separating these images into low-level phase images using multi-phase separation, the gray image can be reconstructed by optical elements which have limited control range. The decrytion process is simply implemented by interfering a multiplication result of encrypted image and key image with reference light. The validity of proposed scheme is verified and the effects, which are caused by phase limitation in decryption process, is analyzed by using computer simulations.

Design of Network Attack Detection and Response Scheme based on Artificial Immune System in WDM Networks (WDM 망에서 인공면역체계 기반의 네트워크 공격 탐지 제어 모델 및 대응 기법 설계)

  • Yoo, Kyung-Min;Yang, Won-Hyuk;Kim, Young-Chon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.35 no.4B
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    • pp.566-575
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    • 2010
  • In recent, artificial immune system has become an important research direction in the anomaly detection of networks. The conventional artificial immune systems are usually based on the negative selection that is one of the computational models of self/nonself discrimination. A main problem with self and non-self discrimination is the determination of the frontier between self and non-self. It causes false positive and false negative which are wrong detections. Therefore, additional functions are needed in order to detect potential anomaly while identifying abnormal behavior from analogous symptoms. In this paper, we design novel network attack detection and response schemes based on artificial immune system, and evaluate the performance of the proposed schemes. We firstly generate detector set and design detection and response modules through adopting the interaction between dendritic cells and T-cells. With the sequence of buffer occupancy, a set of detectors is generated by negative selection. The detection module detects the network anomaly with a set of detectors and generates alarm signal to the response module. In order to reduce wrong detections, we also utilize the fuzzy number theory that infers the degree of threat. The degree of threat is calculated by monitoring the number of alarm signals and the intensity of alarm occurrence. The response module sends the control signal to attackers to limit the attack traffic.

Adaptive Filter Design for Eliminating Baseline Wandering Noise of Electrocardiogram (심전도 기저선 흔들림 잡음 제거를 위한 적응형 필터 설계)

  • Choi, Chul-Hyung;Rahman, MD Saifur;Kim, Si-Kyung;Park, In-Deok;Kim, Young-Pil
    • The Journal of Korean Institute of Information Technology
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    • v.15 no.12
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    • pp.157-164
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    • 2017
  • Mobile ECG signal measurement is a technique to measure small signals of several mV, and many studies have been conducted to remove noise including wandering scheme. Removal of the equipotential line noise caused by shaking or movement of the electrode cable is one of the core research contents for the electrocardiogram measurement. In this study, we proposed a modified step-size of combined NLMS(normalized least squares) and DLMS(delayed least squares) adaptive filter to eliminate baseline noise from ECG signals. The proposed method mainly adjusts initial filter step-size to reduce distortion of original ECG signals characteristic after eliminating baseline noise. The modified filter step-size is scaled by filter order size and distortion minimization factor. This method is suitable for portable ECG device with a small processor and less power consumption. This technique also decreases computation time which is essential for real-time filtering. The proposed filter also increase the signal to noise ratio (SNR) compared to conventional NLMS filter.

On-line Fundamental Frequency Tracking Method for Harmonic Signal and Application to ANC (조화신호의 실시간 기본 주파수 추종 방법과 능동소음제어에의 응용)

  • Kim, Sun-Min;Park, Young-Jin
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 2000.06a
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    • pp.263-268
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    • 2000
  • In this paper, a new indirect feedback active noise control (ANC) scheme based on the fundamental frequency estimation is proposed for systems with a harmonic noise. When reference signals necessary for feedforward ANC configuration is difficult to obtain, the conventional ANC algorithms for multi-tonal noise do not measure the reference signals but generate them with the estimated frequencies. However, the beating phenomena, in which certain frequency components of the noise vanish intermittently, may make the adaptive frequency estimation difficult. The confusion in the estimated frequencies due to the beating phenomena makes the generated reference signals worthless. The proposed algorithm consists of two parts. The first part is a reference generator using the fundamental frequency estimation and the second one is the conventional feedforward control. We propose the fundamental frequency estimation algorithm using decision rules, which is insensitive to the beating phenomena. In addition, the proposed fundamental frequency estimation algorithm has good tracking capability and lower variance of frequency estimation error than that of the conventional cascade ANF method. We are also able to control all interested modes of the noise, even which cannot be estimated by the conventional frequency estimation method because of the poor SIN ratio. We verify the performance of the proposed ANC method through simulations for the measured cabin noise of a passenger ship and the measured time-varying engine booming noise of a passenger vehicle.

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Noise-robust electrocardiogram R-peak detection with adaptive filter and variable threshold (적응형 필터와 가변 임계값을 적용하여 잡음에 강인한 심전도 R-피크 검출)

  • Rahman, MD Saifur;Choi, Chul-Hyung;Kim, Si-Kyung;Park, In-Deok;Kim, Young-Pil
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.18 no.12
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    • pp.126-134
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    • 2017
  • There have been numerous studies on extracting the R-peak from electrocardiogram (ECG) signals. However, most of the detection methods are complicated to implement in a real-time portable electrocardiograph device and have the disadvantage of requiring a large amount of calculations. R-peak detection requires pre-processing and post-processing related to baseline drift and the removal of noise from the commercial power supply for ECG data. An adaptive filter technique is widely used for R-peak detection, but the R-peak value cannot be detected when the input is lower than a threshold value. Moreover, there is a problem in detecting the P-peak and T-peak values due to the derivation of an erroneous threshold value as a result of noise. We propose a robust R-peak detection algorithm with low complexity and simple computation to solve these problems. The proposed scheme removes the baseline drift in ECG signals using an adaptive filter to solve the problems involved in threshold extraction. We also propose a technique to extract the appropriate threshold value automatically using the minimum and maximum values of the filtered ECG signal. To detect the R-peak from the ECG signal, we propose a threshold neighborhood search technique. Through experiments, we confirmed the improvement of the R-peak detection accuracy of the proposed method and achieved a detection speed that is suitable for a mobile system by reducing the amount of calculation. The experimental results show that the heart rate detection accuracy and sensitivity were very high (about 100%).

VLSI Design of Interface between MAC and PHY Layers for Adaptive Burst Profiling in BWA System (BWA 시스템에서 적응형 버스트 프로파일링을 위한 MAC과 PHY 계층 간 인터페이스의 VLSI 설계)

  • Song Moon Kyou;Kong Min Han
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.42 no.1
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    • pp.39-47
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    • 2005
  • The range of hardware implementation increases in communication systems as high-speed processing is required for high data rate. In the broadband wireless access (BWA) system based on IEEE standard 802.16 the functions of higher part in the MAC layer to Provide data needed for generating MAC PDU are implemented in software, and the tasks from formatting MAC PDUs by using those data to transmitting the messages in a modem are implemented in hardware. In this paper, the interface hardware for efficient message exchange between MAC and PHY layers in the BWA system is designed. The hardware performs the following functions including those of the transmission convergence(TC) sublayer; (1) formatting TC PDU(Protocol data unit) from/to MAC PDU, (2) Reed-solomon(RS) encoding/decoding, and (3) resolving DL MAP and UL MAP, so that it controls transmission slot and uplink and downlink traffic according to the modulation scheme of burst profile. Also, it provides various control signal for PHY modem. In addition, the truncated binary exponential backoff (TBEB) algorithm is implemented in a subscriber station to avoid collision on contention-based transmission of messages. The VLSI architecture performing all these functions is implemented and verified in VHDL.

Improved AR-FGS Coding Scheme for Scalable Video Coding (확장형 비디오 부호화(SVC)의 AR-FGS 기법에 대한 부호화 성능 개선 기법)

  • Seo, Kwang-Deok;Jung, Soon-Heung;Kim, Jin-Soo;Kim, Jae-Gon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.12C
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    • pp.1173-1183
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    • 2006
  • In this paper, we propose an efficient method for improving visual quality of AR-FGS (Adaptive Reference FGS) which is adopted as a key scheme for SVC (Scalable Video Coding) or H.264 scalable extension. The standard FGS (Fine Granularity Scalability) adopts AR-FGS that introduces temporal prediction into FGS layer by using a high quality reference signal which is constructed by the weighted average between the base layer reconstructed imageand enhancement reference to improve the coding efficiency in the FGS layer. However, when the enhancement stream is truncated at certain bitstream position in transmission, the rest of the data of the FGS layer will not be available at the FGS decoder. Thus the most noticeable problem of using the enhancement layer in prediction is the degraded visual quality caused by drifting because of the mismatch between the reference frame used by the FGS encoder and that by the decoder. To solve this problem, we exploit the principle of cyclical block coding that is used to encode quantized transform coefficients in a cyclical manner in the FGS layer. Encoding block coefficients in a cyclical manner places 'higher-value' bits earlier in the bitstream. The quantized transform coefficients included in the ealry coding cycle of cyclical block coding have higher probability to be correctly received and decoded than the others included in the later cycle of the cyclical block coding. Therefore, we can minimize visual quality degradation caused by bitstream truncation by adjusting weighting factor to control the contribution of the bitstream produced in each coding cycle of cyclical block coding when constructing the enhancement layer reference frame. It is shown by simulations that the improved AR-FGS scheme outperforms the standard AR-FGS by about 1 dB in maximum in the reconstructed visual quality.

Design of a Low Power Reconfigurable DSP with Fine-Grained Clock Gating (정교한 클럭 게이팅을 이용한 저전력 재구성 가능한 DSP 설계)

  • Jung, Chan-Min;Lee, Young-Geun;Chung, Ki-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.2
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    • pp.82-92
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    • 2008
  • Recently, many digital signal processing(DSP) applications such as H.264, CDMA and MP3 are predominant tasks for modern high-performance portable devices. These applications are generally computation-intensive, and therefore, require quite complicated accelerator units to improve performance. Designing such specialized, yet fixed DSP accelerators takes lots of effort. Therefore, DSPs with multiple accelerators often have a very poor time-to-market and an unacceptable area overhead. To avoid such long time-to-market and high-area overhead, dynamically reconfigurable DSP architectures have attracted a lot of attention lately. Dynamically reconfigurable DSPs typically employ a multi-functional DSP accelerator which executes similar, yet different multiple kinds of computations for DSP applications. With this type of dynamically reconfigurable DSP accelerators, the time to market reduces significantly. However, integrating multiple functionalities into a single IP often results in excessive control and area overhead. Therefore, delay and power consumption often turn out to be quite excessive. In this thesis, to reduce power consumption of dynamically reconfigurable IPs, we propose a novel fine-grained clock gating scheme, and to reduce size of dynamically reconfigurable IPs, we propose a compact multiplier-less multiplication unit where shifters and adders carry out constant multiplications.