• Journal of Korean Society of Industrial and Systems Engineering
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• v.22 no.50
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• pp.23-32
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• 1999

Reliability and maintainability allocation in the analysis of the system's design, with the objective of planning and installing the individual components in such a way that the system performance is achieved. This paper has been made to solve an important task in reliability management of manufacturing systems within the general objective being to increase productivity while maintaining costs low. Thus, the purpose of this paper is to provide an analytical approach to determine an optimal reliability and maintainability allocation, trading off among system performance and parts investment costs. Two important considerations will be addressed in this regard : (ⅰ) determine the reliability and maintainability allocation of parts which maximizes a given production index, having fixed the total cost of investments ; and (ⅱ) determine the reliability and maintainability allocation which minimizes the total cost of investments, having fixed a minimum acceptable level of productivity. The procedure proposed in this paper is able to provide to managers and designers useful indications on the reliability and maintainability characteristics of parts in series -parallel systems. And this heuristic model is a decision support tool for contractors who are involved in large scale design projects such as ship and aircraft design. Numerical examples prove that an approximate expression of the average throughput rate is sufficiently accurate to be used in a numerical optimization method.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.49 no.1
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• pp.119-127
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• 2012

This paper describes development and performance test of signal processor for the millimeter wave seeker. A ground to air guidance missile is required various beam patterns in order to counteract different kind of target. Therefore, we designed the hardware and software architecture considering flexibility. This signal processor consists of ADC, FPGA, DSP and etc. FPGA provides peripheral interface to DSP and convert digital IF signal to baseband signal. DSP performs signal processing, calculates target's information and controls devices. Each parts' hardware are connected in series and signal processing algorithms for various beam patterns are built in parallel.

• Sleep Medicine and Psychophysiology
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• v.15 no.1
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• pp.5-11
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• 2008

Sleep is an essential process maintaining the life cycle of the human. In parallel with physiological, cognitive, subjective, and behavioral changes that take place during the sleep, there are remarkable changes in the electroencephalogram (EEG) that reflect the underlying electro-physiological activity of the brain. However, analyzing EEG and relating the results to clinical observations is often very hard due to the complexity and a huge data amount. In this article, I introduce several linear and non-linear tools, developed to analyze a huge time series data in many scientific researches, and apply them to EEG to characterize various sleep states. In particular, the spectral analysis, detrended fluctuation analysis (DFA), and synchrony analysis are administered to EEG recorded during nocturnal polysomnography (NPSG) processes and daytime multiple sleep latency tests (MSLT). I report that 1) sleep stages could be differentiated by the spectral analysis and the DFA ; 2) the gradual transition from Wake to Sleep during the sleep onset could be illustrated by the spectral analysis and the DFA ; 3) electrophysiological properties of narcolepsy could be characterized by the DFA ; 4) hypnic jerks (sleep starts) could be quantified by the synchrony analysis.

• Journal of Ocean Engineering and Technology
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• v.20 no.4 s.71
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• pp.76-82
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• 2006

The large-eddy simulation(LES) technique, based an a message passing interface method(MPI), was applied to investigate the turbulent flaw phenomena around a ship. The Smagorinski model was used in the present LES simulation to simulate the turbulent flaw around a ship. The SPMD(sidsngle program multiple data) technique was used for parallelization of the program using MPI. All computations were performed an a 24-node PC cluster parallel machine, composed of 2.6 GHz CPU, which had been installed in the Advanced Ship Engineering Research Center(ASERC). Numerical simulations were performed for the Wigley hull, and the Series 60 hull(CB=0.6) using 1/4-, 1/2-, 1- and 2-million grid systems and the computational results had been compared to the experimental ones.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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• 2008.10a
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• pp.249-251
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• 2008

We investigated a flux-coupling type superconducting fault current(SFCL) limiter. The SFCL consisted of the primary and secondary coils, which were wound in series each other through an iron core. Superconducting unit was connected with secondary coil in parallel. The flux generated from a coil in normal operation is cancelled out by its structure and the zero resistance of the superconducting unit. In this paper. In order to compare the current limiting effects of the SFCL by applied voltage. When a lied voltage was increased, quench time was shortened Fast quench time is important component under the same fault condition because power burden of the SFCL is reduced by that of the superconducting units. The current limiting behavior of flux-coupling type SFCL was dependent upon the applied voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.289-289
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• 2008

We investigated the operational characteristics of the separated three-phase flux-lock type superconducting fault current limiter (SFCL). The single-phase lock type SFCL consist of two coils, which are wound in parallel through an iron core. The high-$T_c$ superconducting(HSTC) thin film connected in series with secondary coil. The separated three-phase flux-lock type SFCL consist of three single-phase flux-lock type SFCL. In a normal condition, the SFCL is not operate. When a fault occurs, the current of a HSTC thin film exceeds its critical current by fault current, the resistance of the HSTC thin film generated. Therefore fault current was limited by SFCL. The separated three-phase flux-lock type SFCL are operated in fault condition such as the the single line-to-ground fault, the double line-to-ground fault and the triple line-to-ground fault. The experimental results, the SFCL operational characteristics was dependent on fault condition.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.7
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• pp.515-520
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• 2018

A large number of lithium-ion batteries are arranged in series and parallel in battery packs, such as those in electric vehicles or energy storage systems. As battery packs age, their output power and energy density drop because of voltage deviation, constant and non-uniform exposure to abnormal environments, and increased contact resistance between batteries; this reduces application system efficiency. Despite the balancing circuit and logic of the battery management system, the output of the battery pack is concentrated in the most severely aged unit cell and the output is frequently limited by power derating. In this study, we implemented a cell imbalance detection algorithm and selected parameters to detect a sudden decrease in battery pack output. In addition, we propose a method to increase efficiency by applying the measured testing values considering the operating conditions and abnormal conditions of the battery pack.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.6
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• pp.618-626
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• 2011

Solar cell is one of the most important new renewable energy for future energy generation. This paper presents a novel two stage DC/DC converter topology for PV PCSs. The proposed converter consists of an interleaved boost converter and a two-tank LLC resonant converter which is connected in parallel in primary and series in secondary. The main idea of this topology is that the system can achieve either unilateral or bilateral operations due to the input voltage level of the PV module, which leads to a better performance. The operating schemes on the proposed converter are analyzed and described. A 2.2kW prototype product is built, tested and verified.

• Journal of Power Electronics
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• v.13 no.1
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• pp.20-30
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• 2013

This paper presents a soft switching DC/DC converter for high voltage application. The interleaved pulse-width modulation (PWM) scheme is used to reduce the ripple current at the output capacitor and the size of output inductors. Two converter cells are connected in series at the high voltage side to reduce the voltage stresses of the active switches. Thus, the voltage stress of each switch is clamped at one half of the input voltage. On the other hand, the output sides of two converter cells are connected in parallel to achieve the load current sharing and reduce the current stress of output inductors. In each converter cell, a half-bridge converter with the asymmetrical PWM scheme is adopted to control power switches and to regulate the output voltage at a desired voltage level. Based on the resonant behavior by the output capacitance of power switches and the transformer leakage inductance, active switches can be turned on at zero voltage switching (ZVS) during the transition interval. Thus, the switching losses of power MOSFETs are reduced. The current doubler rectifier is used at the secondary side to partially cancel ripple current. Therefore, the root-mean-square (rms) current at output capacitor is reduced. The proposed converter can be applied for high input voltage applications such as a three-phase 380V utility system. Finally, experiments based on a laboratory prototype with 960W (24V/40A) rated power are provided to demonstrate the performance of proposed converter.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.49 no.5
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• pp.278-286
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• 2000

A new large-scale network geometric analysis is introduced. For a large-scale circuit, it must be analyzed with a geometric diagram and figure. So many equations are induced from a geometric loop-node diagram. The results are arranged into a simple matrix, of course. In case of constructing a network diagram, it is not easy to handle voltage and current sources together. Geometric loop analysis is related to voltage sources, and node analysis is to current sources. The reciprocal transfer is possible only to have series or parallel impedance. If not having this impedance, in order to obtain equivalent circuit, many equations must be derived. In this paper a loop-reduction method is proposed. With this method current source branch is included into the other branch, and disappears in circuit diagram. So the number of independent circuit equations are reduced as much as that of current sources. The number is not (b-n+1), but (b-n+1-p). Where p is the number of current sources. The reduction procedure is verified with a geometric principle and circuit theory. A resultant matrix can be constructed directly from this diagram structure, not deriving circuit equations. We will obtain the last results with the help of a computer.