Development of CPLD Technology Mapping Algorithm for Sequential Circuit Improved Run-Time Under Time Constraint (시간제약 조건하에서 순차 회로를 위한 수행시간을 개선한 CPLD 기술 매핑 알고리즘 개발)
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- Journal of the Institute of Electronics Engineers of Korea SD
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- v.37 no.4
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- pp.80-89
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- 2000