• Journal of the Semiconductor & Display Technology
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• v.6 no.4
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• pp.5-9
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• 2007

Phase transition and dopant redistribution during silicidation of $CoSi_2$ thin films were characterized depending on their preparation methods. Our results indicated that cleanness of the substrate surface played an important role in the formation of the final phase. This effect was found to be reduced by addition of W resulting in the formation of $CoSi_2$. However, even in this case, the formation of the final phase was achieved at the cost of extra thermal energy, which induced rough interface between the substrate and the silicide film. As for the dopant redistribution, the deposition sequence of Co and Si on SiGe was observed to induce significant differences in the dopant profiles. It was found that co-deposition of Co and Si resulted in the least redistribution of dopants thus maintaining the original dopant profile.

• Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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• 2007.11a
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• pp.595-600
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• 2007

This paper presents a new jetting dispenser driven by a piezoelectric actuator at high operating frequency to provide very small dispensing dot size of adhesive in modern semiconductor packaging processes. After describing the mechanism and operational principle of the dispenser, a mathematical model of the structured system is derived by considering behavior of each component such as piezostack and dispensing needle. In the fluid modeling, a lumped parameter method is applied to model the adhesive whose rheological property is expressed by Bingham model. The governing equations are then derived by integrating the structural model with the fluid model. Based on the proposed model, dispensing performances such as dispensing amount are investigated with respect to various input trajectories.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.18 no.4
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• pp.432-438
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• 2008

This paper presents a new jetting dispenser driven by a piezoelectric actuator at high operating frequency to provide very small dispensing dot size of adhesive in modern semiconductor packaging processes. After describing the mechanism and operational principle of the dispenser, a mathematical model of the structured system is derived by considering behavior of each component such as piezostack and dispensing needle. In the fluid modeling, a lumped parameter method is applied to model the adhesive whose rheological property is expressed by Bingham model. The governing equations are then derived by integrating the structural model with the fluid model. Based on the proposed model, dispensing performances such as dispensing amount are investigated with respect to various input trajectories.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.439-442
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• 2001

Chalcogenide glassy semiconductors(CGS) can be obtained by the melt quenching technique. We have investigated the thin film heterostructures : metal-chalcogenide glassy semiconductors, where metal is copper, and chalcogenide glassy semiconductors are glasses of the system As-Se. CU/CGS film heterostructure were produced in the vacuum evaporator by the method of vacuum thermal evaporation. Doped films are very sensitive to external actions, and this property allows developing supersensitive precision sensors of temperature, humidity, illumination, and etc. based on them. Cu/CGS film has shown that resistance strongly depend on the temperature. The ratio of resistance vs. temperature has shown over a 2 k$\Omega$/degree. The slop of temperature and resistance shows linear.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.727-730
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• 2002

Chalcogenide glassy semiconductors(CGS) can be obtained by the melt quenching technique. We have investigated the thin film heterostructures : metal-chalcogenide glassy semiconductors, where metal is copper, and chalcogenide glassy semiconductors are glasses of the system As-Se. Cu/CGS film heterostructure were produced in the vacuum evaporator by the method of vacuum thermal evaporation. Doped films are very sensitive to external actions, and this property allows developing supersensitive precision sensors of temperature, humidity, illumination, and etc. based on them. Cu/CGS film has shown that resistance strongly depend on the temperature. The slop of temperature and resistance shows linear.

• Journal of the Semiconductor & Display Technology
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• v.7 no.3
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• pp.51-54
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• 2008

In this study, we investigated variations in undoped ZnO thin film properties with working pressure, $O_2$/Ar ratio, and annealing ambient. Higher vacuum pressure during deposition was observed to bring about slower growth rate resulting in samples with better crystallinity as well as hole generation efficiency through formation of shallower oxygen interstitial. Given that $O_2$/Ar ratio is greater than unity, O provided from the ambient to ZnO during annealing was found to preferably situate at interstitial sites. When He was used for the second annealing, significant changes were not observed. On the other hand, O ambient caused increased density of oxygen interstitial, thereby making the film more intrinsic-like high resistivity ZnO.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.221-224
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• 2000

We have successfully demonstrated metal-ferroel-ectric-insulator-semiconductor (MFIS) devices using Al/LiNbO$_{3}$/SiN/Si structure. The SiN thin films were made into metal -insulator- semiconductor (MIS) devices by thermal evaporation of aluminum source in a dot away on the surface. The interface property of MFIS from 1MHz & quasistatic C-V is good and the memory window width is about 1.5V at 0.2V/s signal voltage sweep rate. The gate leakage current density of MFIS capacitors using a aluminum electrode showed the least value of 1x10$^{-8}$ A/$\textrm{cm}^2$ order at the electric field of 300㎸/cm. And the XRD patterns shows the probability of applications of LN for MFIS devices for FeRAMs on amorphous SiN buffer layer.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.09a
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• pp.183-192
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• 2001

1- Buildup PCB technology is utilized to a bare chip attach substrate technology for packaging of semiconductor chip 2- Requirement for the substrate design rule is described in SIA International Technology Roadmap for Semiconductor. 3- There are seven fabrication methods of build-up technology. 4- Coating and lamination for resin and photo, and laser for micro via hope processes are available. Below $50\mu\textrm{m}$ in diameter is possible. 5- Fine pitch lines down to $30\mu\textrm{m}$ can be achieved by pattern plating with better electrical property. 6- Dielectric loss reduction is a key material improvement item for next generation build-up technology. 7- High band width up to 512 GB/s is possible with current wiring groundrule.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.5
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• pp.351-354
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• 2013

Thin-film transistors(TFTs) with silicon-zinc-tin-oxide(SiZnSnO, SZTO) channel layer are fabricated by rf sputtering method. Electrical properties were changed by different annealing treatment of dry annealing and wet annealing. This procedure improves electrical property especially, stability of oxide TFT. Improved electrical properties are ascribed to desorption of the negatively charged oxygen species from the surfaces by annealing treatment. The threshold voltage ($V_{th}$) shifted toward positive as increasing Si contents in SZTO system. Because the Si has a lower standard electrode potential (SEP) than that that of Sn, Zn, resulting in the degeneration of the oxygen vacancy ($V_O$). As a result, the Si acts as carrier suppressor and oxygen binder in the SZTO as well as a $V_{th}$ controller, resulting in the enhancement of stability of TFTs.

• Journal of the Semiconductor & Display Technology
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• v.11 no.1
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• pp.67-71
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• 2012

The optical properties of PDP, such as the transmittance and reflectance, were analyzed with 3D optical code. Three different ITO-less structures in the front panel are examined. In the assembled panel study, the test 1 structure shows 16.6% and 10.2% higher reflectance than the structures of tests 2 and 3, respectively. In order to check the validation of the simulation result, three 7.5-inch test panels having the same geometry and property are fabricated as simulation models. The calculated reflective properties are compared to the measured data from real panels. The relative difference extracted from the simulation and measurement methods is less than 4.9% and are well matched.