• Title/Summary/Keyword: semiconductor property

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A Current-controlled CMOS operational transconductance amplifier (전류- 제어 CMOS operational transconductance amplifier)

  • Chung, W.S.;Cha, H.W.;Kim, H.B.;Rho, S.R.
    • Proceedings of the KIEE Conference
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    • 1988.07a
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    • pp.563-566
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    • 1988
  • A current-controlled CMOS operational transconductance amplifier(OTA), whose transconductance is directly proportional to the DC bias current, has been developed for many electronic circuit applications. It features that its transconductance is insensitive to temperature unlike that of the bipolar OTA. This property makes it possible to use the proposed OTA as a basic buliding block in electrically variable circuit design. The SPICE simulation shows that the conversion sensitivity of the circuit is 44.62 mv /${\mu}A$ and the linearity error less than 0.54 % over a bias current range from 2 ${\mu}A$ to 120 ${\mu}A$ when the output is loaded with a 1${\Omega}$ resistor.

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A Study on the Estimation of Economic Service Life on Semiconductor Equipments (반도체 제조설비의 경제적 내용연수 산정)

  • Oh, Hyun-Seung;Kim, Chong-Su;Suh, Jung-Yul;Cho, Jin-Hyung
    • Journal of Korean Society of Industrial and Systems Engineering
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    • v.30 no.4
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    • pp.164-169
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    • 2007
  • The estimation of mortality characteristics of industrial property is an important adjunct to engineering valuation and depreciation estimation. Once the important of depreciation estimation is determined, it is desirable to understand the processes upon which these estimates are based. The Iowa type survivor curves are a set of generalized retirement dispersion models. These curves were based on analysis of actual retirement experience and represent typical retirement behavior patterns likely to be encountered. The retirement rate of Iowa type survivor curves on the semiconductor equipments in Korea industry was estimated by the life estimation process. In this paper, estimates of service lives based on directly observed data of the domestic semiconductor equipments are presented.

Investigation on Electrical Property of Amorphous Oxide SiZnSnO Semiconducting Thin Films (비정질 산화물 SiZnSnO 반도체 박막의 전기적 특성 분석)

  • Byun, Jae Min;Lee, Sang Yeol
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.32 no.4
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    • pp.272-275
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    • 2019
  • We investigated the electrical characteristics of amorphous silicon-zinc-tin-oxide (a-SZTO) thin films deposited by RF-magnetron sputtering at room temperature depending on the deposition time. We fabricated a thin film transistor (TFT) with a bottom gate structure and various channel thicknesses. With increasing channel thickness, the threshold voltage shifted negatively from -0.44 V to -2.18 V, the on current ($I_{on}$) and field effect mobility (${\mu}_{FE}$) increased because of increasing carrier concentration. The a-SZTO film was fabricated and analyzed in terms of the contact resistance and channel resistance. In this study, the transmission line method (TLM) was adopted and investigated. With increasing channel thickness, the contact resistance and sheet resistance both decreased.

A Survey on Property Inference Attack and Defense Technique for Federated Learning Model (연합학습 모델에 대한 특성 추론 공격 및 방어 기법에 대한 연구)

  • Hyun-Jun Kim;Yun-Gi Cho;Yun-Heung Paek
    • Proceedings of the Korea Information Processing Society Conference
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    • 2023.05a
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    • pp.224-226
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    • 2023
  • 본 논문에서는 연합학습 모델을 타겟으로 하는 특성 추론 공격 및 방어 기법과 관련된 연구들을 소개한다. 연합학습 시스템에 특화된 2가지 특성 추론 공격 및 이에 대한 방어 기법들에 대해 정리하고, 향후 연구 방향을 조망하고자 한다.

Crystallographic Characterization of the (Bi, La)4Ti3O12 Film by High-Resolution Electron Microscopy (고분해능 전자현미경법을 이용한 (Bi, La)4Ti3O12 박막의 결정학적 특성 평가)

  • Lee, Doek-Won;Yang, Jun-Mo;Park, Tae-Su;Kim, Nam-Kyung;Yeom, Seung-Jin;Park, Ju-Chul;Lee, Soun-Young;Park, Sung-Wook
    • Korean Journal of Materials Research
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    • v.13 no.7
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    • pp.478-483
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    • 2003
  • The crystallographic characteristics of the $(Bi, La)_4$$Ti_3$$O_{12}$ thin film, which is considered as an applicable dielectrics in the ferroelectric RAM device due to a low crystallization temperature and a good fatigue property, were investigated at the atomic scale by high resolution transmission electron microscopy and the high resolution Z-contrast technique. The analysis showed that a (00c) preferred orientation and a crystallization of the film were enhanced with the diffraction intensity increase of the (006) and (008) plane as the annealing temperature increased. It indicated a change of the atomic arrangement in the (00c) plane. Stacking faults on the (00c) plane were also observed. Through the comparison of the high-resolution Z-contrast image and the $Bi_4$$Ti_3$$O_{12}$ atomic model, it was evaluated that the intensity of the Bi atom was different according to the atomic plane, and it was attributed to a substitution of La atom for Bi at the specific atom position.

Simulation of Junction Field Effect Transistor using SiGe-Si-SiGe Channel Structure (SiGe-Si-SiGe 채널구조를 이용한 JFET 시뮬레이션)

  • Park, B.G.;Yang, H.Y.;Kim, T.S.;Shim, K.H.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.94-94
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    • 2008
  • We have performed simulation for Junction Field Effect Transistor(JFET) using Silvco to improve its electrical properties. The device structure and process conditions of Si-control JFET(Si-JFET) were determined to set its cut off voltage and drain current(at Vg=0V) to -0.5V and $300{\mu}A$, respectively. From electrical property obtained at various implantation energy, dose, and drive-in conditions of p-gate doping, we found that the drive in time of p-type gate was the most determinant factor due to severe diffusion. Therefore we newly designed SiGe-JFET, in which SiGe layer is to epitaxial layers placed above and underneath of the Si-channel. The presence of SiGe layer lessen the p-type dopants (Boron) into the n-type Si channel the phenomenon would be able to enhance the structural consistency of p-n-p junction. The influence of SiGe layer will be discussed in conjunction with boron diffusion and corresponding I-V characteristics in comparison with Si-control JFET.

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Thermal property evaluation of semiconductor laser (반도체 레이저의 열적 특성 평가)

  • 박경현
    • Proceedings of the Optical Society of Korea Conference
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    • 1990.02a
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    • pp.79-81
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    • 1990
  • Temperature distribution of laser diode chip mounted on ideal heat kink was calculated by numerical analysis. In numerical analysis, infinite difference method and Gauss-Scidel iteration was adopted on the basis of two dimensional heat conduction phenomena. As a result, temperature increase of active medium of laser diode driven at 60mA was calculated to be 1.47$^{\circ}C$

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A Study on Improvement and Degradation of Si/SiO2 Interface Property for Gate Oxide with TiN Metal Gate

  • Lee, Byung-Hyun;Kim, Yong-Il;Kim, Bong-Soo;Woo, Dong-Soo;Park, Yong-Jik;Park, Dong-Gun;Lee, Si-Hyung;Rho, Yong-Han
    • Transactions on Electrical and Electronic Materials
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    • v.9 no.1
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    • pp.6-11
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    • 2008
  • In this study, we investigated effects of hydrogen annealing (HA) and plasma nitridation (PN) applied in order to improve $Si/SiO_2$ interface characteristics of TiN metal gate. In result, HA and PN showed a positive effect decreasing number of interface state $(N_{it})$ respectively. After FN stress for verifying reliability, however, we identified rapid increase of $N_{it}$ for TiN gate with HA, which is attributed to hydrogen related to a change of $Si/SiO_2$ interface characteristic. In contrast to HA, PN showed an improved Nit and gate oxide leakage characteristic due to several possible effects, such as blocking of Chlorine (Cl) diffusion and prevention of thermal reaction between TiN and $SiO_2$.

Effects of Electrostatic Discharge Stress on Current-Voltage and Reverse Recovery Time of Fast Power Diode

  • Bouangeune, Daoheung;Choi, Sang-Sik;Cho, Deok-Ho;Shim, Kyu-Hwan;Chang, Sung-Yong;Leem, See-Jong;Choi, Chel-Jong
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.4
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    • pp.495-502
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    • 2014
  • Fast recovery diodes (FRDs) were developed using the $p^{{+}{+}}/n^-/n^{{+}{+}}$ epitaxial layers grown by low temperature epitaxy technology. We investigated the effect of electrostatic discharge (ESD) stresses on their electrical and switching properties using current-voltage (I-V) and reverse recovery time analyses. The FRDs presented a high breakdown voltage, >450 V, and a low reverse leakage current, < $10^{-9}$ A. From the temperature dependence of thermal activation energy, the reverse leakage current was dominated by thermal generation-recombination and diffusion, respectively, at low and high temperature regions. By virtue of the abrupt junction and the Pt drive-in for the controlling of carrier lifetime, the soft reverse recovery behavior could be obtained along with a well-controlled reverse recovery time of 21.12 ns. The FRDs exhibited excellent ESD robustness with negligible degradations in the I-V and the reverse recovery characteristics up to ${\pm}5.5$ kV of HBM and ${\pm}3.5$ kV of IEC61000-4-2 shocks. Likewise, transmission line pulse (TLP) analysis reveals that the FRDs can handle the maximum peak pulse current, $I_{pp,max}$, up to 30 A in the forward mode and down to - 24 A in the reverse mode. The robust ESD property can improve the long term reliability of various power applications such as automobile and switching mode power supply.