• 전력전자학회논문지
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• 제28권1호
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• pp.39-47
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• 2023

This paper applies a structural technique with uniform parallel switch characteristics in gates and power loops to minimize the ringing and current imbalance that occurs when a general discrete package (TO-247)-based power semiconductor device is operated in parallel. Also, this propose a heat sink integrated switching module with heat sink design flexibility and high power density. The developed heat dissipation-integrated switching module verifies the symmetry of the parasitic inductance of the parallel switch through Q3D by ansys and the validity of the structural technique of the parallel switch using the LLC resonant converter experiment operating at a rated capacity of 7.5 kW.

• 한국표면공학회지
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• 제54권5호
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• pp.207-212
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• 2021

The mechanical and electrical characteristics can be improved in 3D stacked IC technology which can accomplish the ultra-high integration by stacking more semiconductor chips within the limited package area through the Cu direct bonding method minimizing the performance degradation to the bonding surface to the inorganic compound or the oxide film etc. The surface was treated in a ultrasonic washer using a diamond abrasive to remove other component substances from the prepared cast plate substrate surface. FE-SEM was used to analyze the bonding characteristics of the bonded copper substrates, and the cross section of the bonded Cu conjugates at the sintering junction temperature of 100 ℃, 150 ℃, 200 ℃, 350 ℃ and the pressure of 2303 N/cm² and 3087 N/cm². At 2303 N/cm², the good bonding of copper substrate was confirmed at 350 ℃, and at the increased pressure of 3087 N/cm², the bonding condition of Cu was confirmed at low temperature junction temperature of 200 ℃. However, the recrystallization of Cu particles was observed due to increased pressure of 3087 N/cm² and diffusion of Cu atoms at high temperature of 350 ℃, which can lead to degradation in semiconductor manufacturing.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2001년도 추계학술대회 논문집
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• pp.139-143
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• 2001

In manufacturing process of semiconductor package, thermal stress owing to high temperature in moulding and bubbles generated in chip bonding process become main causes to producing void. Therefore, on this study we evaluated quantitatively void size by ultrasonic spectroscopy method which analyze the frequency of this received pulse using pulses with broad band frequency, and after destructive test we verified effectiveness of sizing void by ultrasonic spectroscopy as we find error degree between the real size of void and the sizing void by ultrasonic spectroscopy.

• 오토저널
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• 제14권5호
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• pp.107-116
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• 1992

Recently, it is gradually raised necessity that interface is measured accurately and managed in industrial circle and medical world. An Ultrasonic wave transmitted from a focused beam tranducer is being expected as a powerful tool for NDE of the delamination. The Ultrasonic NDE of the delamination is based on the form of the wave reflected from the interface. In this study results, automatically repeated discrimination analysis method can be devided in the category of all kinds of defects on semiconductor package, and also can be possible to have a sampling of partial delamination.

• 비파괴검사학회지
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• 제10권2호
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• pp.43-49
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• 1990

Ultrasonic testing is one of the most useful NDT method for detection of microdefect in the opaque materials. Recently, many applications of the ultrasonic techniques have been extended widely in the new field like electron is and advanced materials. From the result of the experiment, we have hardly found out a crack in the internal parts of the resin and a delamination between chip and resin because of poor performance of the system.

• 한국표면공학회지
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• 제8권2호
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• pp.1-6
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• 1975

A novel electroplating process is described and effects of anode lay-out thickness distribution and on platiting rate are discussed. Microphotograhic analysis indicates are compact and less "POROUS " than of barrel and rack. With this process production cost reduction and capacity increase could be achieved by a rate of 60% and 97% respectively, as compared to our present barrel plating process. This process disclose a number of beneficial processes such as color coding system on TO-92 package and development of a new tin bath formula.

• 한국산학기술학회논문지
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• 제15권10호
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• pp.5906-5911
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• 2014

요즈음 생산되는 반도체의 제품이 제대로 작동하는지, 낮은 습도 또는 높은 온도에서 잘 견디는가를 검사하는 패키지 조립 및 검사 공정이 현장에 많이 있다. 또한 검사공정에서 사용되고 있는 반도체 테스트 핸들러 픽커 검사장비가 있는데, 본 연구에서는 CATIA 프로그램을 이용하여 3D 모델링하였으며, ANSYS 프로그램을 이용하여 반도체 테스트 핸들러 픽커 검사장비 프레임의 모델에 대하여 3가지 피로하중에 대한 해석을 하였다. 해석 결과로서 Case 1과 Case 2 모두 프레임의 가운데에서 최대 변형량이 발생하고 불규칙 피로 하중들 중에서 가장 하중의 변동이 심한 'SAE bracket history'가 가장 불안정하고 'Sample history'가 가장 안정함을 보이고 있다. 본 연구의 피로 해석 결과는 반도체 테스트 핸들러 픽커 검사장비 프레임의 파손방지 및 내구성을 검토함으로서 그 프레임의 설계에 효율적으로 활용이 될 수 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.301-306
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• 2015

An ultra-compact and wideband low noise amplifier (LNA) in a quad flat non-leaded (QFN) package is presented. The LNA monolithic microwave integrated circuit (MMIC) is implemented in a $0.25{\mu}m$ GaN IC technology on a Silicon Carbide (SiC) substrate provided by Triquint. A source degeneration inductor and a gate inductor are used to obtain the noise and input matching simultaneously. The resistive feedback and inductor peaking techniques are employed to achieve a wideband characteristic. The LNA chip is mounted in the $3{\times}3-mm^2$ QFN package and measured. The supply voltages for the first and second stages are 14 V and 7 V, respectively, and the total current is 70 mA. The highest gain is 13.5 dB around the mid-band, and -3 dB frequencies are observed at 0.7 and 12 GHz. Input and output return losses ($S_{11}$ and $S_{22}$) of less than -10 dB measure from 1 to 12 GHz; there is an absolute bandwidth of 11 GHz and a fractional bandwidth of 169%. Across the bandwidth, the noise figures (NFs) are between 3 and 5 dB, while the output-referred third-order intercept points (OIP3s) are between 26 and 28 dBm. The overall chip size with all bonding pads is $1.1{\times}0.9mm^2$. To the best of our knowledge, this LNA shows the best figure-of-merit (FoM) compared with other published GaN LNAs with the same gate length.

• 한국항해항만학회지
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• 제27권2호
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• pp.217-221
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• 2003

본 논문에서는 새로운 형태의 CSP (chip site package)를 이용하여 정합소자 린 바이어스소자를 MMIC상에 완전집적한 Ku/K밴드 광대역 증폭기 MMIC에 관하여 보고한다. 새로운 형태의 CSP에 대해서는 이방성 도전필름인 ACF (anisotropic conductive film)을 이용하였으며, 그 결과 MMIC 패키지 프로세스가 간략화 되었고, CSP MMIC의 저 가격화가 실현되었다. MMIC상에 집적하기 위한 DC 바이어스 용량소자로서는 고유전율의 STO (SrTiO3) 필름 커패시터가 이용되었다. 제작된 CSP MMIC는 광대역 RF동작특성 (12-24 GHz에서 12.5$\pm$1.5 dB의 이득치, -6 dB이하의 반사계수, 18.5$\pm$1.5 dBm의 PldB) 을 보였다. 본 논문은 K 또는 Ku 밴드의 주파수대역에 있어서의 완전집적화 CSP MMIC에 관한 최초의 보고이다.

• 융합신호처리학회논문지
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• 제25권1호
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• pp.46-51
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• 2024

드론은 최초 군사용으로 사용되었으나 최근들어 사용범위가 확대됨에 따라 농업, 서비스, 물류, 레져용 등 다양한 산업분야에서 폭넓게 사용되어지고 있는 추세이다. 리튬폴리머 배터리는 경량이면서 효율이 우수하여 드론의 전원공급 장치로 주로 사용되고 있다. 이에따라 드론에 안정적인 전원공급을 위하여 경량이면서 에너지 밀도가 높은 리튬폴리머 배터리의 필요성이 커지게 되었다. 그러나 리튬폴리머 배터리는 과충전, 과방전, 단락 등의 이유로 발화 및 폭발로 이어질 수 있어 반드시 보호회로를 탑제하여 사용해야한다. 보호회로는 리튬폴리머 배터리의 전압을 모니터링하는 제어IC인 보호 IC와 과방전시 스위치 역할을 하는 듀얼 N-channel MOSFET 등으로 구성되어있다. 따라서 본 논문은 배터리 보호 IC와 스위치 역학을 하는 MOSFET의 반도체 Die Chip을 이용하여 원칩 패키지 IC형태로 구현하였다. 원칩 패키지 IC로 구현하면 기존 부품 대비 최소 67%의 절감효과를 갖게된다.