• Journal of the Semiconductor & Display Technology
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• v.22 no.2
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• pp.56-63
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• 2023

This paper presents a method using finite element analysis and topology optimization to address the issue of overdesign in pressure-explosion proof enclosure doors for semiconductor manufacturing processes. The design conducted in this paper focuses on the pattern design of the enclosure door and its fixation components. The process consists of a solid-filled model, a topology optimization model, and a post-processing model. By applying environmental conditions to each model and comparing the maximum displacement, maximum equivalent stress, and weight values, it was confirmed that a reduction of about 13% in weight is achievable.

• Transactions on Electrical and Electronic Materials
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• v.8 no.1
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• pp.1-4
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• 2007

This paper discusses two approaches for pre-polishing optimization of oxide chemical mechanical planarization (CMP) that can be used as alternatives to the commonly applied dummy structure insertion in shallow trench isolation (STI) and replacement gate (RG) technologies: reverse nitride masking (RNM) and oxide etchback (OEB). Wafers have been produced using each optimization technique and CMP tests have been performed. Dishing, erosion and global planarity have been investigated with the help of conductive atomic force microscopy (C-AFM). The results demonstrate the effectiveness of both techniques which yield excellent planarity without dummy structure related performance degradation due to capacitive coupling.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.353-356
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• 2004

This paper discribes the analysis of the I-V characteristics of 4H-SiC DiMOSFET with single epi-layer Silicon Carbide has been around for over a century. However, only in the past two to three decades has its semiconducting properties been sufficently studied and applied, especially for high-power and high frequency devices. We present a numerical simulation-based optimization of DiMOSFET using the general-purpose device simulator MINIMIS-NT. For simulation, a loin thick drift layer with doping concentration of $5{\times}10^{15}/cm^3$ was chosen for 1000V blocking voltage design. The simulation results were used to calculate Baliga's figure of Merit (BFOM) as the criterion structure optimization and comparison.

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.78.1-78
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• 1998

• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.107-113
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• 2024

Scheduling of semiconductor test facilities has been crucial since effective scheduling contributes to the profits of semiconductor enterprises and enhances the quality of semiconductor products. This study aims to solve the scheduling problems for the wafer burn-in test facilities of the semiconductor back-end process by utilizing simulation and deep reinforcement learning-based methods. To solve the scheduling problem considered in this study. we propose novel state, action, and reward designs based on the Markov decision process. Furthermore, a neural network is trained by employing the recent RL-based method, named proximal policy optimization. Experimental results showed that the proposed method outperformed traditional heuristic-based scheduling techniques, achieving a higher due date compliance rate of jobs in terms of total job completion time.

• Korean Management Science Review
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• v.32 no.4
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• pp.69-80
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• 2015

The semiconductor industry is one of those in which the most intricate processes are involved and there are many critical factors that are controlled with precision in those processes. Naturally production scheduling in the semiconductor industry is also very complex and studied by the industry and academia for many years; however, still there are many issues left unclear in the problem. This paper proposes an multi-objective optimization-based scheduling method for semiconductor fabrication(fab). Two main objectives are throughput maximization and meeting target production quantities. The first objective aims to reduce production cost, especially the fixed cost incurred by a large investment constructing a new fab facility. The other is meeting customer orders on time and also helps a fab maintain stable throughput through controlled WIP balancing in the long run. The paper shows a trade-off structure between the two objectives through experimental studies, which provides industrial practitioners with useful references.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.61-66
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• 2009

We have investigated the noise sensitivity of low noise amplifier (LNA) at different frequency. This noise sensitivity analysis provides insights about noise parameters and it is very beneficial for making appropriate design trade-offs. From this work, the circuit designer can choose the adequate noise parameters tolerances.

• Journal of the Semiconductor & Display Technology
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• v.14 no.1
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• pp.39-43
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• 2015

This paper is to derive information about the optimal shape of the pack has a minimum temperature range of a Li-ion battery equipped with a module. We selected the shape of the pack in order to reduce the temperature deviation between the batteries as a variable. And we derived the experimental points with a minimum of DOE by D-optimal. We analyzed the temperature and the flow within the battery pack by using a numerical analysis verified in previous studies. We derive the equation for the temperature variation in the objective function using the RSM and performed optimization. As a result, it was confirmed that with the variation in the $1.706e-4^{\circ}C$ when to apply an optimized shape.

• Journal of the Semiconductor & Display Technology
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• v.16 no.2
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• pp.79-84
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• 2017

This paper outlines the Taguchi optimization methodology, which is applied to optimize cutting parameters in end milling when machining STS304 with TiAlN coated SKH59 tool under up and down end milling conditions. The end milling parameters evaluated are depth of cut, spindle speed and feed rate. An orthogonal array, signal-to-noise (S/N) ratio and analysis of variance (ANOVA) are employed to analyze the effect of these end milling parameters. The Taguchi design is an efficient and effective experimental method in which a response variable can be optimized, given various control and noise factors, using fewer resources than a factorial design. An orthogonal array of $L_9(33)$ was used. The most important input parameter for cutting force, however, is the feed rate, and depending on the cutter rotation direction. Finally, confirmation tests verified that the Taguchi design was successful in optimizing end milling parameters for cutting force.

• Journal of the Semiconductor & Display Technology
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• v.21 no.4
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• pp.163-167
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• 2022

In this paper, an optimization design method of a diffuser using Bernoulli's theorem was reviewed. The aspect ratio of the cylindrical diffuser chamber and the diameter ratio of the air inlet and outlet were used as design parameters. For the optimal design of the cylindrical diffuser chamber, the air flow inside the chamber was simulated using ANSYS while changing the aspect ratio of the chamber. In order to confirm the simulation results, the diffuser manufactured using the laser processing machine was measured. Through ANSYS simulation and measurement, it was found that the optimal design condition was when the aspect ratio (chamber height/radius) of the diffuser chamber was 1/2 and the diameter ratio of the air inlet and outlet was also 1/2.