• Journal of the Korean Crystal Growth and Crystal Technology
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• v.32 no.2
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• pp.55-60
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• 2022

In this study, a heat treatment experiment was conducted to select a new melt composition that can easily control the unintentionally doped nitrogen (N-UID) without degrading the SiC single crystal quality during TSSG process. The experiment was carried out for about 2 hours at a temperature of 1900℃ under Ar atmosphere. The used melt composition is based on either Si-Ti 10 at% or Si-Cr 30 at%, and also Co or Sc transition metals, which are effective for carbon solubility, were added at 3 at%, respectively. After the experiment, the crucible was cross-sectionally cut, and evaluated the Si-C reaction layer on the crucible-melt interface. As a result, with Sc addition, Si-C reaction layers uniformly occurred with a Si-infiltrated layer (~550 ㎛) and a SiC interlayer (~23 ㎛). This result represented that the addition of Sc is an effective transition metal with high carbon solubility and can feed carbon sources into the melt homogeneously. In addition, Sc is well known to have low reactivity energy with nitrogen compared to other transition metals. Therefore, we expect that both growth rate and Nitrogen UID can be controlled by Si-Sc based melt in the TSSG process.

• Current Photovoltaic Research
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• v.7 no.4
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• pp.125-129
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• 2019

Recently, carrier-selective contact solar cells have attracted much interests because of its high efficiency with low recombination current density. In this study, we investigated the effect of phosphorus doped amorphous silicon layer's characteristics on the passivation properties of tunnel oxide passivated carrier-selective contact solar cells. We fabricated symmetric structure sample with poly-Si/SiOx/c-Si by deposition of phosphorus doped amorphous silicon layer on the silicon oxide with subsequent annealing and hydrogenation process. We varied deposition temperature, deposition thickness, and annealing conditions, and blistering, lifetime and passivation quality was evaluated. The result showed that blistering can be controlled by deposition temperature, and passivation quality can be improved by controlling annealing conditions. Finally, we achieved blistering-free electron carrier-selective contact with 730mV of i-Voc, and cell-like structure consisted of front boron emitter and rear passivated contact showed 682mV i-Voc.

• Journal of Digital Convergence
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• v.15 no.9
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• pp.211-221
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• 2017

The semiconductor industry develops and maintains software embedded in computer-controlled tools and facilities, to process and manufacture high-tech products. Upgrading embedded softwares for semiconductor processing robots and machinery is one of the basic activities that must be performed in order to maintain product quality and integrity. Maintenance and enhancement of embedded software consume a major portion of the total life cycle cost of a system. However, the area has been given little attention in the literature. 502 maintenance and enhancement cases, related to embedded softwares in wafer processing machines, were selected at random for analysis. Practical implications are also discussed.

• Journal of the Korean Society of Industry Convergence
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• v.7 no.3
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• pp.259-263
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• 2004

In the manufacture progress of LCD or semiconductor, there are used many kinds of gas like erosion gas, dilution gas, toxic gas as a progress which used these gas there are required high puritize to increase accumulation rate of semiconductor or LCD materials work progress of semiconductor or LCD it demand many things like the material which could minimize metallic dust that could be occured by reaction between gas and transfer pipe laying material, illumination of the surface, emition of the gas, metal liquation, welding etc also demand quality geting stricted. Material-Low-sulfur-contend (0.007-0010), vacuum-arc-remelt(VAR), seamless, high-purity tubing material is recommend for enhance welding lower surface defect density All wetted stainless steel surface must be 316LSS elecrto polishinged with ${\leq}0.254{\mu}m$($10.0{\mu}in$) Ra average surface finish, $Cr/Fe{\geq}1.1$ and $Cr_2O_3$ thickness ${\geq}25{\AA}$ From the AES analytical the oxide layer thickness (23.5~36 angstroms silicon dioxide equivalent) and chromum to iron ratios is similar to those generally found on electropolished stainless steel., molybdenum and silicon contaminants ; elements characteristic of stainless steel (iron, nickel and chromium); and oxygen were found on the surface Phosphorus and nitrogen are common contaminants from the electropolish and passivation steps.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.28 no.4
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• pp.159-165
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• 2018

The demand on use of GaN single crystal substrates for high efficient and environment - friended high power electronic semiconductor has be increased. The industrial business trend on GaN substrate along with its research activities has been reviewed through the recent scientific and technical in formations on the basic of Yole report (2013). The research on the GaN single crystal substrate has been performed continuously for the purpose of the high quality and larger diameter, but its market has not been activated yet.

• Transactions on Electrical and Electronic Materials
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• v.5 no.4
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• pp.138-142
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• 2004

This paper presents the improved bum-in method for the reliability of SRAM in Multi Chip Package (MCP). Semiconductor reliability is commonly improved through the bum-in process. Reliability problem is more significant in MCP that includes over two chips in a package, because the failure of one chip (SRAM) has a large influence on the yield and quality of the other chips - Flash Memory, DRAM, etc. Therefore, the quality of SRAM must be guaranteed. To improve the quality of SRAM, we applied the improved wafer level bum-in process using multi cells selection method in addition to the previously used methods. That method is effective in detecting special failure. Finally, with the composition of some kind of methods, we could achieve the high quality of SRAM in Multi Chip Package.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.101.1-101.1
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• 2016

Van der Waals (vdW) heterostructures built from two-dimensional layered materials provide an unprecedented opportunity in designing new material systems because the lack of dangling bonds on the vdW surfaces enables the creation of high-quality heterointerfaces without the constraint of atomically precise commensurability. In particular, the ability to build artificial heterostructures, combined with the recent advent of transition metal dichalcogenides, allows the fabrication of unique semiconductor heterostructures in an ultimate thickness limit for fundamental studies as well as novel device applications. In this talk, we will present the characterization of the electronic and optoelectronic properties of atomically thin p-n junctions consisting of vertically stacked WSe2 and MoS2 monolayers. We observed gate-tunable diode-like current rectification and a photovoltaic response across the p-n interface. Unlike conventional bulk p-n junctions, the tunneling-assisted interlayer recombination of the majority carriers is responsible for the tenability of the charge transport and the photovoltaic response. Furthermore, we will discuss the enhanced optoelectronic characteristics in graphene-sandwiched vdW p-n junctions.

• Journal of the Semiconductor & Display Technology
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• v.10 no.3
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• pp.61-65
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• 2011

The capabilities of finite elements codes allow now accurate simulations of blanking processes when appropriate materials modelling are used. Over the last decade, numerous numerical studies have focused on the influence of process parameters such as punch-die clearance, tools geometry and friction on blanking force and blank profile. In this study, three dimensional finite element analysis is carried out to design a lead frame blanking die using LS-Dyna3D package. After design of the blanking die, an experiment is also carried out to investigate the characteristics of blanking for nickel alloy Alloy42, a kind of IC lead frame material. In this paper, it has been researched the investigation to examine the influence of process parameters such as clearance and air cylinder pressure on the accuracy of sheared plane. Through the experiment results, it is shown that the quality of sheared plane is less affected by clearance and air cylinder pressure.

• Journal of the Semiconductor & Display Technology
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• v.7 no.1
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• pp.35-40
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• 2008

In OLED vacuum evaporation process, the essential requirements include good uniformity of the film thickness over a glass substrate. And, it is commercially significant to improve the consuming efficiency of material of the evaporant which is deposited on the substrate because of high price of organic materials. In this paper, to achieve the better thickness uniformity and the better organic material consuming rate, a process optimization algorithm was developed by understanding vacuum evaporation process parameters that affect the material consuming efficiency and the uniformity of film thickness. Based on the method developed in this study, the vacuum evaporation process of OLED was successfully controlled. The developed method allowed the manufacture of high quality OLED displays with cheaper fabrication cost.

• Journal of the Semiconductor & Display Technology
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• v.15 no.3
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• pp.6-11
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• 2016

Silicon wafer is one of main materials in solar cell. Micro-cracks in silicon wafer are one of reasons to decrease efficiency of energy transformation. They couldn't be observed by human eye. Also, their shape is not only various but also complicated. Accordingly, their shape classification is absolutely needed for manufacturing process quality and its feedback. The performance of typical classification techniques which is principal component analysis(PCA), neural network, fusion model to integrate PCA with neural network, and support vector machine(SVM), are evaluated using pattern features of micro-cracks. As a result, it has been confirmed that the SVM gives good results in micro-crack classification.