• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.54-58
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• 2023

In this study, we compared the detection accuracy of the parameters of the scaffold failure detection model. A detection algorithm based on convolutional neural network was used to construct a failure detection model for scaffold. The parameter properties of the model were changed and the results were quantitatively verified. The detection accuracy of the model for each parameter was compared and the parameter with the highest accuracy was identified. We found that the activation function has a significant impact on the detection accuracy, which is 98% for softmax.

• Proceedings of the Korea Information Processing Society Conference
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• 2023.11a
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• pp.1167-1168
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• 2023

차량용 반도체 수요의 증가로 자율 주행 및 전장제품에 시스템 반도체 수요가 증가하고 있다. 차량용 반도체는 기존 AP 같은 칩보다 더 높은 내구성과 신뢰성이 요구되기 때문에 불량 분석이 중요하다. 이러한 환경에서 반도체의 안정적인 생산과 품질 보장을 위해서는 불량 검출과 불량 원인 분석이 중요하다. 본 논문은 기본적인 비파괴 불량 분석 방법에 대하여 조사하고 장단점을 탐구한다. 이를 통해 반도체의 안정적인 양산을 위한 기반 지식을 제공한다.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.2
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• pp.35-41
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• 2011

Recently, board level solder joint reliability performance of IC packages during drop impact becomes a great concern to semiconductor and electronic product manufacturers. The handheld electronic products are prone to being dropped during their useful service life because of their size and weight. The IC packages are susceptible to solder joint failures, induced by a combination of printed circuit board (PCB) bending and mechanical shock during impact. The board level drop testing is an effective method to characterize the solder joint reliability performance of miniature handheld products. In this paper, applying the JEDEC (JESD22-B111) standard present a finite element modeling of the FBGA. The simulation results revealed that maximum stress was located at the outermost solder ball in the PCB or IC package side, which consisted well with the location of crack initiation observed in the failure analysis after drop reliability tests.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.1
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• pp.45-51
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• 2004

We have proposed a new shallow trench isolation (STI) process using flowable oxide (F-oxide) chemical vapor deposition (CVD) for DRAM application and it was successfully developed. The combination of F-oxide CVD and HDP CVD is thought to be the superior STI gap-filling process for next generation DRAM fabrication because F-oxide not only improves STI gap-filling capability, but also the reduced local stress by F-oxide in narrow trenches leads to decrease in junction leakage and gate induced drain leakage (GIDL) current. Finally, this process increased data retention time of DRAM compared to HDP STI. However, a serious failure occurred by symphonizing its structural dependency of deposited thickness with poor resistance against HF chemicals. It could be suppressed by reducing the flow time during F-oxide deposition. It was investigated collectively in terms of device yield. In conclusion, the combination of F-oxide and HDP oxide is the very promising technology for STI gap filling process of sub-100nm DRAM technology.

• Journal of the Korean Society of Safety
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• v.17 no.4
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• pp.94-100
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• 2002

As the use of automatic handling equipment for sensitive semiconductor devices is rapidly increased, manufacturers of electronic components and equipments need to be more alert to the problem of electrostatic discharges(ESD). In order to analyze damage characteristics of semiconductor device damaged by ESD, this study adopts a new charged-device model(CDM), field-induced charged model(FCDM) simulator that is suitable for rapid, routine testing of semiconductor devices and provides a fast and inexpensive test that faithfully represents ESD hazards in plants. High voltage applied to the device under test is raised by the field of non-contacting electrodes in the FCDM simulator, which avoids premature device stressing and permits a faster test cycle. Discharge current and time are measured and calculated. The characteristics of electrostatic attenuation of domestic semiconductor devices are investigated to evaluate the ESD phenomena in the semiconductors. Also, the field charging mechanism, the device thresholds and failure modes are investigated and analyzed. The damaged devices obtained in the simulator are analyzed and evaluated by SEM. The results obtained in this paper can be used to prevent semiconductor devices form ESD hazards and be a foundation of research area and industry relevant to ESD phenomena.

• International Journal of Precision Engineering and Manufacturing
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• v.8 no.3
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• pp.50-53
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• 2007

Improving the reliability or long-term dependability of a system requires a different approach from the previous emphasis on short-term concerns. The purpose of this paper is to present a reliability evaluation method for an oil cooler intended for high-precision machining centers. The oil cooler system in question is a cooling device that minimizes the deformation caused from the heat generated by driving devices. This system is used for machine tools and semiconductor equipment. We predicted the reliability of the system based on the failure rate database and conducted the reliability test using a test-bed to evaluate the life of the oil cooler. The results provided an indication of the reliability of the system in terms of the failure rate and the MTBF of the oil cooler system and its components, as well as a distribution of the failure mode. These results will help increase the reliability of oil cooler systems. The evaluation method can also be used to determine the reliability of other machinery products.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.302-308
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• 2011

In this paper, we have proposed a new approach for optical failure analysis which employs a CMOS photon-emitting circuitry, consisting of a flip-flop based on a sense amplifier and a photon-emitting device. This method can be used even with deep-submicron processes where conventional optical failure analyses are difficult to use due to the low sensitivity in the near infrared (NIR) region of the spectrum. The effectiveness of our approach has been proved by the failure analysis of a prototype designed and fabricated in 0.18 ${\mu}m$ CMOS process.

• Transactions on Electrical and Electronic Materials
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• v.17 no.4
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• pp.196-200
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• 2016

We have developed new electrostatic discharge (ESD) protection devices with, bidirectional flip chip transient voltage suppression. The devices differ in their epitaxial (epi) layers, which were grown by reduced pressure chemical vapor deposition (RPCVD). Their ESD properties were characterized using current-voltage (I-V), capacitance-voltage (C-V) measurement, and ESD analysis, including IEC61000-4-2, surge, and transmission line pulse (TLP) methods. Two BD-FCTVS diodes consisting of either a thick (12 μm) or thin (6 μm), n-Si epi layer showed the same reverse voltage of 8 V, very small reverse current level, and symmetric I-V and C-V curves. The damage found near the corner of the metal pads indicates that the size and shape of the radius governs their failure modes. The BD-FCTVS device made with a thin n- epi layer showed better performance than that made with a thick one in terms of enhancement of the features of ESD robustness, reliability, and protection capability. Therefore, this works confirms that the optimization of device parameters in conjunction with the doping concentration and thickness of epi layers be used to achieve high performance ESD properties.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.202-211
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• 2014

The bulk current injection (BCI) and direct power injection (DPI) method have been established as the standards for the electromagnetic susceptibility (EMS) test. Because the BCI test uses a probe to inject magnetically coupled electromagnetic (EM) noise, there is a significant difference between the power supplied by the radio frequency (RF) generator and that transferred to the integrated circuit (IC). Thus, the immunity estimated by the forward power cannot show the susceptibility of the IC itself. This paper derives the real injected power at the failure point of the IC using the power transfer efficiency of the BCI method. We propose and mathematically derive the power transfer efficiency based on equivalent circuit models representing the BCI test setup. The BCI test is performed on I/O buffers with and without decoupling capacitors, and their immunities are evaluated based on the traditional forward power and the real injected power proposed in this work. The real injected power shows the actual noise power level that the IC can tolerate. Using the real injected power as an indicator for the EMS test, we show that the on-chip decoupling capacitor enhances the EM noise immunity.

• Journal of the Korean Society for Precision Engineering
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• v.17 no.7
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• pp.217-225
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• 2000

Scanning Acoustic Microscope (SAM) is used as an important nondestructive test tool in semiconductor reliability evaluation and failure analysis. However, inspections of chip attach adhesive interface fer thin chip has proven difficulty as the reflected signals from the chip top and bottom are superimposed. In this paper, in order to overcome this difficulty, a new signal processing method based on the deconvolution technique combined with the wavelet transform is proposed. The wavelet transform complements a disability of deconvolution technique of which performance largely decreases when the waveform of target signal is not identical to that of reference signal. Performances of the proposed method are demonstrated by through computer simulations using model signal and experiments for the fabricated semiconductor samples, and satisfactory results are obtained.