• International Journal of Quality Innovation
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• 제8권1호
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• pp.137-153
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• 2007

Failure mode and effects analysis (FMEA) is a preventive technique in reliability management field. The successful implementation of FMEA technique can avoid or reduce the probability of system failure and achieve good product quality. The FMEA technique had applied in vest scopes which include aerospace, automatic, electronic, mechanic and service industry. The marking process is one of the back ends testing process that is the final process in semiconductor process. The marking process failure can cause bad final product quality and return although is not a primary process. So, how to improve the quality of marking process is one of important production job for semiconductor testing factory. This research firstly implements FMEA technique in laser marking process improvement on semiconductor testing factory and finds out which subsystem has priority failure risk. Secondly, a CCD position solution for priority failure risk subsystem is provided and evaluated. According analysis result, FMEA and CCD position implementation solution for laser marking process improvement can increase yield rate and reduce production cost. Implementation method of this research can provide semiconductor testing factory for reference in laser marking process improvement.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권1호
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• pp.34-40
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• 2012

We have developed a highly sensitive inspection technique based on an electron beam inspection for detecting the contact failure of a poly-Si plugged layer. It was difficult to distinguish the contact failure from normal landing plugs with high impedance. Normally, the thermal annealing method has been used to decrease the impedance of poly-Si plugs and this method increases the difference of charged characteristics and voltage contrast. However, the additional process made the loss of time and broke down the device characteristics. Here, the interval scanning method without thermal annealing was effectively applied to enhance the difference of surface voltage between well-contacted poly-Si plugs and incomplete contact plugs. It is extremely useful to detect the contact failures of non-annealed plug contacts with high impedance.

• 한국안전학회지
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• 제15권4호
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• pp.62-68
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• 2000

Static electricity in electronics manufacturing plants causes the economic loss, yet it is one of the least understood and least recognized effects haunting the industry today. Today's challenge in semiconductor devices is to achieve greater functional density pattern and to miniaturize electronic systems of being more fragile by electrostatic discharges(ESD) phenomena. As the use of automatic handling equipment for static-sensitive semiconductor components is rapidly increased, most manufacturers need to be more alert to the problem of ESD. One of the most common causes of electrostatic damage is the direct transfer of electrostatic charge from the human body or a charged material to the static-sensitive devices. To evaluate the ESD hazards by charged human body and devices, in this paper, characteristics of electrostatic attenuation in domestic semiconductor devices is investigated and the voltage to cause electronic component failures is investigated by field-induced charged device model(FCDM) tester. The FCDM simulator provides a fast and inexpensive test that faithfully represents ESD hazards in plants. Also the results obtained in this paper can be used for the prevention of semiconductor failure from ESD hazards.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권3호
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• pp.153-166
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• 2003

Failure analysis is fundamental to the design and development methodology of electrostatic discharge (ESD) devices and ESD robust circuits. The role of failure analysis (FA) in the models, methodology, band mechanisms evaluation for improving ESD robustness of semiconductor products in CMOS, silicon-on-insulator (SOI) and silicon germanium (SiGe) technologies will be reviewed.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.703-706
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• 2003

Yield enhancement in semiconductor fabrication is important. It is ideal to prevent all the failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasure. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. This paper describes the techniques to automatically classifies a failure pattern using a fail bit map, a new simple schema which facilitates the failure analysis.

• 반도체디스플레이기술학회지
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• 제21권4호
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• pp.65-70
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• 2022

In manufacturing and semiconductor industries, transfer robots increase productivity through accurate and continuous work. Due to the nature of the semiconductor process, there are environments where humans cannot intervene to maintain internal temperature and humidity in a clean room. So, transport robots take responsibility over humans. In such an environment where the manpower of the process is cutting down, the lack of maintenance and management technology of the machine may adversely affect the production, and that's why it is necessary to develop a technology for the machine failure diagnosis system. Therefore, this paper tries to identify various causes of failure of transport robots that are widely used in semiconductor automation, and the Prognostics and Health Management (PHM) method is considered for determining and predicting the process of failures. The robot mainly fails in the driving unit due to long-term repetitive motion, and the core components of the driving unit are motors and gear reducer. A simulation drive unit was manufactured and tested around this component and then applied to 6-axis vertical multi-joint robots used in actual industrial sites. Vibration data was collected for each cause of failure of the robot, and then the collected data was processed through signal processing and frequency analysis. The processed data can determine the fault of the robot by utilizing machine learning algorithms such as SVM (Support Vector Machine) and KNN (K-Nearest Neighbor). As a result, the PHM environment was built based on machine learning algorithms using SVM and KNN, confirming that failure prediction was partially possible.

• 대한안전경영과학회지
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• 제8권1호
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• pp.17-26
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• 2006

Basis frame-work's base in a semiconductor industry have gas, chemical, electricity and various facilities in bring to it. That it is a foundation by fire, power failure, blast, spill of toxicant huge by large size accident human and physical loss and damage because it can bring this efficient, connect with each kind mechanical, physical thing to prevent usefully need that control finding achievement factor of human factor of human action. Large size accident in a semiconductor industry to machine and human and it is involved that present, in system by safety interlock defect of machine is conclusion for error of behaviour. What is not construing in this study, do safety in a semiconductor industry to do improvement. Control human error analyzes in human control with and considers mechanical element and several elements. Also, apply achievement factor using O'conner Model by control method of human error. In analyze by failure mode effect using actuality example.

• Transactions on Electrical and Electronic Materials
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• 제12권1호
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• pp.16-19
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• 2011

The oxide-nitride-oxide (ONO) deposition process was added to the beginning of a 0.25 ${\mu}m$ embedded polysiliconoxide-nitride-oxide-silicon (SONOS) process before all of the logic well implantation processes in order to maintain the characteristics of basic CMOS(complementary metal-oxide semiconductor) logic technology. The system subsequently suffered severe ONO rupture failure. The damage was caused by the ONO implantation and was responsible for the ONO rupture failure in the embedded SONOS process. Furthermore, based on the experimental results as well as an implanted ion's energy loss model, processes primarily producing permanent displacement damages responsible for the ONO rupture failure were investigated for the embedded SONOS process.

• Journal of Power Electronics
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• 제16권4호
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• pp.1426-1437
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• 2016

In different industrial and mission oriented applications, redundant or standby semiconductor systems can be implemented to improve the reliability of power electronics equipment. The proper structure for implementation can be one of the redundant or standby structures for series or parallel switches. This selection is determined according to the type and failure rate of the fault. In this paper, the reliability and the mean time to failure (MTTF) for each of the series and parallel configurations in two redundant and standby structures of semiconductor switches have been studied based on different failure rates. The Markov model is used for reliability and MTTF equation acquisitions. According to the different values for the reliability of the series and parallel structures during SC and OC faults, a comprehensive comparison between each of the series and parallel structures for different failure rates will be made. According to the type of fault and the structure of the switches, the reliability of the switches in the redundant structure is higher than that in the other structures. Furthermore, the performance of the proposed series and parallel structures of switches during SC and OC faults, results in an improvement in the reliability of the boost dc/dc converter. These studies aid in choosing a configuration to improve the reliability of power electronics equipment depending on the specifications of the implemented devices.

• 한국시뮬레이션학회논문지
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• 제8권3호
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• pp.49-66
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• 1999

Semiconductor wafer fabrication is known to be one of the most complex manufacturing processes due to process intricacy, random yields, product diversity, and rapid changing technologies. In this study we are concerned with the impact of lot release and dispatching policies on the performance of semiconductor wafer fabrication facilities. We consider several semiconductor wafer fabrication environments according to the machine failure types such as no failure, normal MTBF, bottleneck with low MTBF, high randomness, and high MTBF cases. Lot release rules to be considered are Deterministic, Poisson process, WR(Workload Regulation), SA(Starvation Avoidance), and Multi-SA. These rules are combined with several dispatching rules such as FIFO (First In First Out), SRPT (Shortest Remaining Processing Time), and NING/M(smallest Number In Next Queue per Machine). We applied the combined policies to each of semiconductor wafer fabrication environments. These policies are assessed in terms of throughput and flow time. Basically Weins fabrication setup was used to make the simulation models. The simulation parameters were obtained through the preliminary simulation experiments. The key results throughout the simulation experiments is that Multi-SA and SA are the most robust rules, which give mostly good performance for any wafer fabrication environments when used with any dispatching rules. The more important result is that for each of wafer fabrication environments there exist the best and worst choices of lot release and dispatching policies. For example, the Poisson release rule results in the least throughput and largest flow time without regard to failure types and dispatching rules.