• Transactions of the Korean Society of Mechanical Engineers B
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• v.41 no.6
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• pp.409-414
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• 2017

The aim of this study is to understand the phonon transfer characteristics of a silicon thin film transistor. For this purpose, the Joule heating mechanism was considered through the electron-phonon interaction model whose validation has been done. The phonon transport characteristics were investigated in terms of phonon mean free path for the variations in the device power and silicon layer thickness from 41 nm to 177 nm. The results may be used for developing the thermal design strategy for achieving reliability and efficiency of the silicon-on-insulator (SOI) transistor, further, they will increase the understanding of heat conduction in SOI systems, which are very important in the semiconductor industry and the nano-fabrication technology.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• Journal of the Korean Electrochemical Society
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• v.10 no.2
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• pp.94-103
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• 2007

The transition of interconnection metal from aluminum alloy to copper has been introduced to meet the requirements of high speed, ultra-large scale integration, and high reliability of the semiconductor device. Since copper, which has low electrical resistivity and high resistance to degradation, has different electrical and material characteristics compared to aluminum alloy, new related materials and processes are needed to successfully fabricate the copper interconnection. In this review, some important factors of multilevel copper damascene process have been surveyed such as diffusion barrier, seed layer, organic additives for bottom-up electro/electroless deposition, chemical mechanical polishing, and capping layer to introduce the related issues and recent research trends on them.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.39 no.10
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• pp.1011-1019
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• 2015

Insulated-gate bipolar transistors (IGBTs) are the predominantly used power semiconductors for high-current applications, and are used in trains, airplanes, electrical, and hybrid vehicles. IGBT power modules generate a considerable amount of heat from the dissipation of electric power. This heat generation causes several reliability problems and deteriorates the performances of the IGBT devices. Therefore, thermal management is critical for IGBT modules. In particular, realizing a proper thermal design for which the device temperature does not exceed a specified limit has been a key factor in developing IGBT modules. In this study, we investigate the thermal behavior of the 1200 A, 3.3 kV IGBT module package using finite-element numerical simulation. In order to minimize the temperature of IGBT devices, we analyze the effects of various packaging materials and different thickness values on the thermal characteristics of IGBT modules, and we also perform a design-of-experiment (DOE) optimization

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.1
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• pp.51-58
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• 2016

As semiconductor technology has developed, device performance has been improved. However, since device structures became smaller, circuit aging due to operational and environmental conditions can be accelerated. Circuit aging causes a performance degradation and eventually a system error. In reliable systems, a failure due to aging might cause a great disaster. Therefore, these systems need a performance degradation prediction function so that they can take action in advance before a failure occurs. This paper presents an on-line circuit performance degradation monitoring scheme for predicting a failure by detecting performance degradation during circuit normal operation. In our proposed scheme, IEEE 1149.1 output boundary scan cells and TAP controller are reused. The experimental result shows that the proposed architecture can monitor the performance degradation during normal operation without stopping the circuit.

• Journal of the Korean Vacuum Society
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• v.2 no.2
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• pp.188-198
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• 1993

We have developed a technique for growing thin oxides (6~10 nm) by the Last step TCA method. N-channel metal-oxide-semiconductor (n-MOS) capacitor and n-channel metal-oxide-semiconductor field-effect transistor's (MOSFET's) having a gate oxide with chlorine incorporated $SiO_2/Si$ interface have been analyzed by electrical measurements and physical methods, such as secondary ion mass spectrometry (SIMS) and electron spectroscopy for chemical analysis (ESCA). The gate oxide grown with the Last strp TCA method has good characteristics as follows: the electron mobility of the MOSFET's with the Last step TCA method was increased by about 7% and the defect density at the $SiO_2/Si$ interface decreases slightly compared with that with No TCA method. In reliability estimation, the breakdown field was 18 MV/cm, 0.6 MV/cm higher than that of the gate oxide with No TCA method, and the lifetime estimated by TDDB measurement was longer than 20 years. The device lifetime estimated from hot-carrier reliability was proven to be enhanced. As the results, the gate oxide having a $SiO_2/Si$ interface incorporated with chlorine has good characteristics. Our new technique of Last step TCA method may be used to improve the endurance and retention of MOSFET's and to alleviate the degradation of thin oxides in short-channel MOS devices.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.34 no.1
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• pp.1-7
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• 2024

β-Ga₂O₃ is a material with a wide band gap of ~4.8 eV and a high breakdown-voltage of 8 MV/cm, and is attracting much attention in the field of power device applications. In addition, compared to representative WBG semiconductor materials such as SiC, GaN and Diamond, it has the advantage of enabling single crystal growth with high growth rate and low manufacturing cost [1-4]. In this study, we succeeded in growing a 10 mm thick β-Ga₂O₃ single crystal doped with 0.3 mol% SnO₂ through the EFG (Edge-defined Film-fed Growth) method using multi-slit structure. The growth direction and growth plane were set to [010]/(010), respectively, and the growth speed was about 12 mm/h. The grown β-Ga₂O₃ single crystal was cut into various crystal planes (010, 001, 100, ${\bar{2}}01$) and surface processed. The processed samples were compared for characteristics according to crystal plane through analysis such as XRD, UV/VIS/NIR/Spec., Mercury Probe, AFM and Etching. This research is expected to contribute to the development of power semiconductor technology in high-voltage and high-temperature applications, and selecting a substrate with better characteristics will play an important role in improving device performance and reliability.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.1-9
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• 2010

Three-dimensional (3-D) integration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip to form highly integrated micro-nano systems. Since CMOS device scaling has stalled, 3D integration technology allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. The potential benefits of 3D integration can vary depending on approach; increased multifunctionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. It is expected that the semiconductor industry's paradiam will be shift to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D based technologies in highly integrated systems. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of IT-NT-BT systems. This paper attempts to introduce new 3D integration technologies of the chip self-assembling stacking and 3D heterogeneous opto-electronics integration for realizng the super-chip.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.12 no.2
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• pp.120-126
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• 2019

Recently, there is an increasing need for highly precise processing with the rapid development of precision machinery, electrical and electronics, and semiconductor industries. Cutting machine control relies on the operator's sense and experience in tradition, but it has been greatly enhanced by the adoption of CNC(Computerized Numeric Controller). In addition, cutting dynamics technology has been paid attention to reflect the operating state of machine in real time. This paper presents a method to detect and stabilize tool vibration by attaching an acoustic sensor to a CNC machine. The sensed acoustic data is synchronized with the tool position and the abnormal vibration frequency is separated from the collected acoustic frequency, then analyzed to detect the tool vibration. Also the reliability the tool vibration detection and stabilization is improved by applying the cutting dynamic method. The proposed method is analyzed and evaluated in terms of the surface roughness.

• Current Photovoltaic Research
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• v.4 no.3
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• pp.108-113
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• 2016

III-V compound semiconductor based thin film solar cells promise relatively higher power conversion efficiencies and better device reliability. In general, the thin film III-V solar cells are fabricated by an epitaxial lift-off process, which requires an $Al_xGa_{1-x}As$ ($x{\geq}0.8$) sacrificial layer and an inverted solar cell structure. However, the device performance of the inversely grown solar cell could be degraded due to the different internal diffusion conditions. In this study, InGaP/GaAs double-junction solar cells are inversely grown by MOCVD on GaAs (100) substrates. The thickness of the GaAs base layer is reduced to minimize the thermal budget during the growth. A wide band gap p-AlGaAs/n-InGaP tunnel junction structure is employed to connect the two subcells with minimal electrical loss. The solar cell structures are transferred on to thin metal films formed by Au electroplating. An AlAs layer with a thickness of 20 nm is used as a sacrificial layer, which is removed by a HF:Acetone (1:1) solution during the epitaxial lift-off process. As a result, the flexible InGaP/GaAs solar cell was fabricated successfully with an efficiency of 27.79% under AM1.5G illumination. The efficiency was kept at almost the same value after bending tests of 1,000 cycles with a radius of curvature of 10 mm.