• Proceedings of the Korea Water Resources Association Conference
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• 2006.05a
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• pp.546-551
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• 2006

It considered the population decrease and becoming older in age of the Rural area and operates by unmaned-non power which self-controlled gate developed. The operational principal used a buoyancy and when water level in the canal arrived to the set water level, in order for gate to be opened. The plate in order to fix to the shape in the canal which begs, it did in the quadrilateral and the rainfall it is sour intensively, canal bank comfort plate in order to ascend completely, it designed. The result which establishes Self-controlled gate, the gate upstream 1km until degree there was water level synergistic effect. It developed 4 as the research project and it established in Ah San city, and it establishes the Self-controlled gate of $B3.2m{\times}H2.4m$ size in Damyang and 100ha it does water supply in the rice field.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.2
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• pp.77-79
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• 1992

We propose a self-aligned and double recessed technique for GaAs power MESFETs application. The gate length and the wide recess width are defined by a selective removal of the SiN layer using reactive ion etching(RIE) while the depth of the channel is defined by chemical etching of GaAs layers. The threshold voltages and the saturation drain voltage could be sucessfully controlled using this technique. The lateral-etched distance increases with the dry etching time and the source-drain breakdown voltage of MESFET increases up to about 30V at a pinch-off condition. The electrical characteristics of a MESFET with a gate length of 2 x10S0-6Tm and a source-gate spacing of 33 x10S0-6Tm show maximum transconductance of 120 mS/mm and saturation drain current density of 170-190mA/mm at a gate voltage of 0.8V.

• Journal of Adhesion and Interface
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• v.23 no.2
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• pp.53-58
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• 2022

Here, the surface characteristics of the dielectric were controlled by introducing the self-assembled monolayers (SAMs) as the intermediate layers on the surface of the AlOx dielectric, and the electrical performances of the organic charge modulated transistor (OCMFET) were significantly improved. The organic intermediate layer was applied to control the surface energy of the AlOx gate dielectric acting as a capacitor plate between the control gate (CG) and the floating gate (FG). By applying the intermediate layers on the gate dielectric surface, and the field-effect mobility (μ_OCMFET) of the OCMFET devices could be efficiently controlled. We used the four kinds of SAM materials, octadecylphosphonic acid (ODPA), butylphosphonic acid (BPA), (3-bromopropyl)phosphonic acid (BPPA), and (3-aminopropyl)phosphonic acid (APPA), and each μ_OCMFET was measured at 0.73, 0.41, 0.34, and 0.15 cm2V-1s-1, respectively. The results could be suggested that the characteristics of each organic SAM intermediate layer, such as the length of the alkyl chain and the type of functionalized end-group, can control the electrical performances of OCMFET devices and be supported to find the optimized fabrication conditions, as an efficient sensing platform device.

• Journal of Power Electronics
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• v.17 no.4
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• pp.1117-1126
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• 2017

The main contribution of this paper is the use of sensorless active diodes to generate the gate signals for a three-phase boost-rectifier with a self-powered control scheme. The sensorless operation is achieved making use of the gate control signals generated by the active diode schemes on each of the switching devices using a pulse width half-controlled boost rectifier modulation technique (PWM-HCBR). The proposed scheme synchronizes the gate control signals with a three phase voltage supply. Autonomous operation is obtained making use of the output DC bus to feed the control circuitry, the active diodes and the driver circuitry. The three-phase boost-rectifier is supplied by a three-phase permanent magnet electric generator powered by a solar concentrator dish with variable voltage and variable frequency conditions. Experimental results report an efficiency of up to 94.6% for 25 W and an input of 3.6 V peak per phase with 450.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.276-276
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• 2014

High-performance, fully-transparent, and top-gated oxide thin-film transistor (TFT) was successfully fabricated with Ta2O5 high-k gate dielectric on a glass substrate. Through a self-passivation with the gate dielectric and top electrode, the top-gated oxide TFT was not affected from H2O and O2 causing the electrical instability. Heat-treated InSnO (ITO) was used as the top and source/drain electrode with a low resistance and a transparent property in visible region. A InGaZnO (IGZO) thin-film was used as a active channel with a broad optical bandgap of 3.72 eV and transparent property. In addition, using a X-ray diffraction, amorphous phase of IGZO thin-film was observed until it was heat-treated at 500 oC. The fabricated device was demonstrated that an applied electric field efficiently controlled electron transfer in the IGZO active channel using the Ta2O5 gate dielectric. With the transparent ITO electrodes and IGZO active channel, the fabricated oxide TFT on a glass substrate showed optical transparency and high carrier mobility. These results expected that the top-gated oxide TFT with the high-k gate dielectric accelerates the realization of presence of fully-transparent electronics.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.54-61
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• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.2
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• pp.140-145
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• 2002

A new CMOS buffer removing short-circuit power consumption is proposed. The gate-driving signal of the pull-up(pull-down) transistor at the output is controlled by delayed internal signal to get tri-state output momentarily by shunting off the path of the short-circuit current. The SPICE simulation results verified the operation of the proposed buffer and showed the enhancement of the power-delay product at 3.3V supply voltage about 42% comparing to the conventional tapered CMOS buffer(1).

• Journal of the Korean Vacuum Society
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• v.7 no.2
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• pp.88-93
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• 1998

The fabrication process and emission characteristics of gated silicon field emitter arrays(FEAs) using chemical-mechanical-polishing (CMP) method are described. Novel fabrication techniques consisting of two-step dry etching with oxidation of silicon and CMP processes were developed for the formation of sharp tips and clear-cut edged gate electrodes, respectively. The gate height and aperture could be easily controlled by varying the polishing time and pressure in the CMP process. We obtained silicon FEAs having self-aligned and clear-cut edged gate electrode opening by eliminating the dishing problem during the CMP process with an oxide mask layer. The tip height of the finally fabricated FEAs was about 1.1 $\mu$m and the end radius of the tips was smaller than 100 $\AA$. The emission current meaured from the fabricated 2809 tips array was about 31 $\mu$A at a gate voltage of 80 V.

• Journal of Power Electronics
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• v.5 no.2
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• pp.109-119
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• 2005

This paper deals with the performance analysis of static compensator (STATCOM) based voltage regulator for self­excited induction generators (SEIGs) supplying balanced/unbalanced and linear/ non-linear loads. In practice, most of the loads are linear. But the presence of non-linear loads in some applications injects harmonics into the generating system. Because an SEIG is a weak isolated system, these harmonics have a great effect on its performance. Additionally, SEIG's offer poor voltage regulation and require an adjustable reactive power source to maintain a constant terminal voltage under a varying load. A three-phase insulated gate bipolar transistor (IGBT) based current controlled voltage source inverter (CC- VSI) known as STATCOM is used for harmonic elimination. It also provides the required reactive power an SEIG needs to maintain a constant terminal voltage under varying loads. A dynamic model of an SEIG-STATCOM system with the ability to simulate varying loads has been developed using a stationary d-q axes reference frame. This enables us to predict the behavior of the system under transient conditions. The simulated results show that by using a STATCOM based voltage regulator the SEIG terminal voltage can be maintained constant and free from harmonics under linear/non linear and balanced/unbalanced loads.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.202-207
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• 1997

Design and fabrication issues for an L-band GaAs Monolithic Microwave Integrated Circuit(MMIC) Voltage Controlled Oscillator(VCO) as a component of Personal Communications Systems(PCS) Radio Frequency(RF) transceiver are discussed. An ion-implanted GaAs MESFET tailored toward low current and low noise with 0.5mm gate length and 300mm gate width has been used as an active device, while an FET with the drain shorted to the source has been used as the voltage variable capacitor. The principal design was based on a self-biased FET with capacitive feedback. A tuning range of 140MHz and 58MHz has been obtained by 3V change for a 600mm and a 300mm devices, respectively. The oscillator output power was 6.5dBm wth 14mA DC current supply at 3.6V. The phase noise without any buffer or PLL was 93dB/1Hz at 100KHz offset. Harmonic balance analysis was used for the non-linear simulation after a linear simulation. All layout induced parasitics were incorporated into the simulation with EEFET2 non-linear FET model. The fabricated circuits were measured using a coplanar-type probe for bare chips and test jigs with ceramic packages.