• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.1 no.1
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• pp.1-9
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• 2002

In this paper, a DRO (Dielectric Resonator Oscillator) with high stability in DSRC(Dedicated Short Range Communication) is designed and fabricated. The DRO shows the phase noise characteristic of -109.3 dBc/Hz at 100 kHz offset from the fundamental frequency. The output power of 11.53 dBm, and the second harmonic suppression of 55.33 dBc for the DRO are obtained. This DRO with high stability of the phase noise characteristic can be used for the system in DSRC.

• Proceedings of the Korean Society of Medical Physics Conference
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• 2002.09a
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• pp.367-369
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• 2002

We have designed ramp profile excitation pulse based on the Shinnar-Le Roux (SLR) algorithm. The algorithm provides many advantages to pulse designers. The first advantage is the freedom of deciding the amplitudes, frequencies, and ripple sizes of stopband, passband, and transition band of pulse profile. The second advantage is the freedom of deciding the pulse phase, more specifically, minimum phase, linear phase, maximum phase, and any phase between them. The minimum phase pulse is the best choice in the case of 3D TOF, because it minimizes the echo time, which implies the best image quality in the same MR examination condition. In addition, the half echo technique is slightly modified in our case. In general, using the half echo technique means that the acquired data size is half and the rest part can be filled with complex conjugate of acquired data. But in our case, the echo center is just shifted to left, which implies the reduction of echo time, and the acquired data size is the same as the one without using the half echo technique. In this case, the increase of right part of data leads to improvement of the resolution and the decrease of left part of data leads to decrease of signal to noise ratio. Since in the case of 3D TOF, the signal to noise ratio is sufficiently high and the resolution is more important than signal to noise ratio, the proposed method appears to be significantly affective and gives rise to the improved high resolution angiograms.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.9
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• pp.1083-1089
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• 2007

In this paper, we applied the CMRC to a resonator to improve the harmonic characteristic of VCO. The CMRC filters have some advantage. It is a small size as well as easy to manufacture than PBG, DGS and other filters. This paper was proposed by using CMRC for a VCO. The second harmonic of -42.83 dBc and the phase noise at 100 kHz offset of -95.83 dBc/Hz was achieved, respectively. The VCO has better second harmonic character by 15.73 dB and phase noise by 31.13 dB in case of CMRC applied behind a resonator than CMRC used as a resonator.

• Journal of the Korean Institute of Telematics and Electronics
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• v.15 no.5
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• pp.13-18
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• 1978

A delay switching PLL (DSPLL) is proposed for improvement of the frequency acquisition Performance (pull-in range) while keeping a narrow bandwidth LPF. It has, between the phase detector and the LPF, just a simple RC delay circuit, a switch and another phase detector controlling the switching time. For the common second order PLL, the pull-in capability of the DSPLL is analyzed approximately, without considering additive white noise effect, and verified experimentally. It is shown that the delay switching extends the pull-in range significantly, as much as a half of lock-range. At the phase tracking mode, the delay switching does not function, to make the DSPLL be a normal PLL.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.15 no.1 s.94
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• pp.29-38
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• 2005

The track pull-in behavior analysis in an optical disk drive (ODD) using plane phase and the evaluations for effecting parameters of it are discussed. Track pull-in, track capture procedure to do track following control, is a key factor to increase data transfer rate. First, the relative velocity between the beam spot of an optical pick-up and the target track of an optical disk is analyzed during the track pull-in procedure. In this process, it is showed that the track error signal has nonlinear characteristics which are depending on the time. Second, Runge-Kutta method to solve the nonlinear equation is applied to find the track pull-in behavior, and some optimal parameters to get stable and fast pull-in condition are obtained. Then, the phase plane analysis for track pull-in procedure is presented. Finally, some comments for the simulated results are discussed briefly.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.127-128
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• 2006

The proposed differential LC cross-coupled VCO is implemented in InGap/GaAs HBT process for an adaptive Global Positioning system(GPS) application. Two filtering capacitors are used at the base of output buffer amplifiers at the both sides of the core m order to improve phase noise characteristics. The VCO produced a phase noise of -133 dBc/Hz at 3MHz offset frequency from the carrier frequency of 1.489GHz and the second harmonic suppression is significantly suppresed up to -49dBc/Hz in simulation result. The three pairs of BC diodes are integrated m the tank circuit to increase the VCO Tunning range.

• Journal of the Korean Institute of Intelligent Systems
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• v.9 no.6
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• pp.571-576
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• 1999

We consider a class of auto-associative memories namely N-Cubes (Neural-network Cubes) in which 2-D gray-level images and hidden sinusoidal 1-D wavelets are stored in cubical memories. First we develop a learning procedure based upon the least-squares algorithm, Therefore each 2-D training image is mapped into the associated 1-D waveform in the training phase. Second we show how the recall procedure minimizes errors among the orthogonal basis functions in the hidden layer. As a 2-D images ould be retrieved in the recall phase. Simulation results confirm the efficiency and the noise-free properties of N-Cubes.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.4
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• pp.421-427
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• 2004

A low cost solution employing harmonic oscillation to the frequency synthesizer at 5.8 ㎓ is proposed. The proposed frequency synthesizer is composed of 2.9 ㎓ PLL chip, 2.9 ㎓ oscillator, and 5.8 ㎓ buffer amplifier The measured data shows a frequency Outing range of 290 ㎒, ranging from 5.65 to 5.94 ㎓ about 0.5 ㏈m of output power, and a phase noise of -107.67 ㏈c/㎐ at the 100 ㎑ offset frequency. All spurious signals including fundamental oscillation power(2.9 ㎓) are suppressed at least 15 ㏈c than the desired second harmonic signal.

• Proceedings of the IEEK Conference
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• 1998.06a
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• pp.106-109
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• 1998

Wireless communication systems, in particular, must operate in a crowded electro-magnetic environmnet where in-band undesired signals are treated as noise by the receiver. These interfering signals are often random but not Gaussian Due to nongaussian noise, the distribution of the observables cannot be specified by a finite set of parameters; instead r-dimensioal sample space (pure noise samples) is equiprobably partitioned into a finite number of disjointed regions using quantiles and a vector quantizer based on training samples. If we assume that the detected symbols are correct, then we can observe the pure noise samples during the training and transmitting mode. The algorithm proposed is based on a piecewise approximation to a regression function based on quantities and conditional partition moments which are estimated by a RMSA (Robbins-Monro Stochastic Approximation) algorithm. In this paper, we develop a diversity combiner with modified detector, called Non-Linear Detector, and the receiver has a differential phase detector in each diversity branch and at the combiner each detector output is proportional to the second power of the envelope of branches. Monte-Carlo simulations were used as means of generating the system performance.

• Journal of IKEEE
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• v.17 no.3
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• pp.248-253
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• 2013

Frequency detector is a circuit that converts the frequency to a digital representation and finds its application in various fields such as modulator and synchronization circuitry. In this paper, a couple of first-order and second-order frequency discriminator structures are modeled and analyzed with their quantization noise sources. Also a delta-sigma frequency detector architecture is proposed. Through theoretical analysis and derived equations, the output noise is obtained, which is validated by simulation. The proposed all-digital frequency discriminator may be applied in the feedback path of the all-digital phase-locked loop.