• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.215-220
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• 2016

Monolithically integrated devices are strongly desired in next generation power ICs to reduce the chip size and improve the efficiency and frequency response. Three examples of the embedment of different functional diode(s) into AlGaN/GaN heterojunction field-effect transistors are presented, which can minimize the parasitic effects caused by interconnection between devices.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.179-182
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• 2007

Polycrystaline (poly) 3C-SiC thin film on n-type and p-type Si were deposited by APCVD using HMDS, $H_2$, and Ar gas at $1180^{\circ}C$ for 3 hour. And then the schottky diode with Au/poly 3C-Sic/Si(n-type) structure was fabricated. Its threshold voltage ($V_d$), breakdown voltage, thickness of depletion layer, and doping concentration ($N_D$) value were measured as 0.84 V, over 140 V, 61nm, and $2.7{\times}10^{19}\;cm^3$, respectively. The p-n junction diode fabricated by poly 3C-SiC was obtained like characteristics of single 3C-SiC p-n junction diode. Therefore, its poly 3C-SiC thin films are suitable MEMS applications in conjuction with Si fabrication technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.66-70
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• 2003

In this paper a plannar singly balanced diode Miter for 24GHz band application is designed and implemented using a microstrip line and two schottky barrier beam lead mixer diodes. The implemented mixer have a conversion loss of 6 [dB], LO/RF isolation of 23 [dB], input 1dB compression point of 4 [dBm]. this diode mixer would be useful for homedyne radar.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.7
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• pp.486-493
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• 2003

Schottky type A $l_{0.33}$G $a_{0.67}$N ultraviolet photodetectors were fabricated on the MOCVD grown AlGaN/ $n^{＋}$-GaN and AlGaN/AlGaN interlayer/ $n^{＋}$-GaN structures. The grown layers have the carrier concentrations of -$10^{18}$, and the mobilities were 236 and 269 $\textrm{cm}^2$/V.s, respectively. After mesa etching by ICP etching system, the Si3N4 layer was deposited for passivation between the contacts and Ti/AL/Ni/Au and Pt were deposited for ohmic and Schottky contact, respectively. The fabricated Pt/A $l_{0.33}$G $a_{0.67}$N Schottky diode revealed a leakage current of 1 nA for samples with interlayer and 0.1$\mu\textrm{A}$ for samples without interlayer at a reverse bias of -5 V. In optical measurement, the Pt/A $l_{0.33}$G $a_{0.67}$N diode with interlayer showed a cut-off wavelength of 300 nm, a prominent responsivity of 0.15 A/W at 280 nm and a UV-visible extinction ratio of 1.5x$10^4./TEX>.

• ETRI Journal
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• v.38 no.2
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• pp.244-251
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• 2016

In this paper, we investigate the electrical characteristics of two trench-gate-type super-barrier rectifiers (TSBRs) under different p-body implantation conditions (low and high). Also, design considerations for the TSBRs are discussed in this paper. The TSBRs' electrical properties depend strongly on their respective p-body implantation conditions. In the case of the TSBR with a low p-body implantation condition, it exhibits MOSFET-like properties, such as a low forward voltage ($V_F$) drop, high reverse leakage current, and a low peak reverse recovery current owing to a majority carrier operation. However, in the case of the TSBR with a high p-body implantation condition, it exhibits pn junction diode.like properties, such as a high $V_F$, low reverse leakage current, and high peak reverse recovery current owing to a minority carrier operation. As a result, the TSBR with a low p-body implantation condition is capable of operating as a MOSFET, and the TSBR with a high p-body implantation condition is capable of operating as either a pn junction diode or a MOSFET, but not both at the same time.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.305-305
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• 2010

It is known that a pulse of electrons of high kinetic energy (1-3 eV) in metals can be generated with the deposition of external energy to the surface such as in the absorption of light or in exothermic chemical processes. These energetic electrons are not in thermal equilibrium with the metal atoms and are called "hot electrons" The concept of photon energy conversion to hot electron flow was suggested by Eric McFarland and Tang who directly measured the photocurrent on gold thin film of metal-semiconductor ($TiO_2$) Schottky diodes [1]. In order to utilize this scheme, we have fabricated metal-semiconductor Schottky diodes that are made of Pt or Au as a metallic layer, Si or $TiO_2$ as a semiconducting substrate. The Pt/$TiO_2$ and Pt/Si Schottky diodes are made by PECVD (Plasma Enhanced Chemical Vapor Deposition) for $SiO_2$, magnetron sputtering process for $TiO_2$, e-beam evaporation for metallic layers. Metal shadow mask is made for device alignment in device fabrication process. We measured photocurrent on Pt/n-Si diodes under AM1.5G. The incident photon to current conversion efficiency (IPCE) at different wavelengths was measured on the diodes. We also show that the steady-state flow of hot electrons generated from photon absorption can be directly probed with $Pt/TiO_2$ Schottky diodes [2]. We will discuss possible approaches to improve the efficiency of photon energy conversion.

• Journal of the Korean Vacuum Society
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• v.16 no.3
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• pp.197-204
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• 2007

Ultra thin Er-silicide layers formed by Er deposition on the clean p-silicon and in situ post annealing technique were investigated with respect to change of the Schottky barrier height. The formation of Er silicides was confirmed by XPS results. UPS measurements revealed that the workfunction of the silicide decreased and was saturated as the deposited Er thickness increased up to $10{\AA}$. We found that the silicides were mainly composed of Er5Si3 phase through the XRD experiments. After Schottky diodes were fabricated with the Er silicide/p-Si junctions, the Schottky barrier heights were calculated $0.44{\sim}0.78eV$ from the I-V measurements of the Schottky diodes. There was large discrepancy in the Schottky barrier heights deduced from the UPS with the ideal junction condition and the real I-V measurements, so that we attributed the discrepancy to the $Er_5Si_3$ phase in the Er-silicides and the large interfacial density of trap state of it.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.771-774
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• 2003

Passivation Ledge's device is taken possession on one-side to the Emitter in this Paper. contact used in this paper Pt as Passivation Ledge of device to use Schottky Diode which has leitmotif, It is accomplished Current Modulation that we wish to do purpose using this device. Space Charge acts as single device which is becoming Passivation to know this phenomenon. This device becomes floating as well as Punched-through. V$_{L}$ (Voltage for Ledge) = - 0.5V ~ 0.5V variable values , PD(Partially Depleted ; Λ＞0), as seeing FD(Fully Depleted ; A = 0) maximum electric current gains and Gummel Plot of I-V characteristics (V$_{L}$ = 0.1/ V$_{L}$ = -0.1 ). Becomming Degradation under more than V$_{L}$ = 0.1 , less than V$_{L}$ =-0.05 and Maximum Gain(=98.617076 A/A) value in the condition V$_{L}$ = 0.1. A Change of Modulation is electric current gains by using Schottky Diode and Extrinsic Base PN Diode of Passivation Ledge to Emitter Depletion Layer in HBT of Gummel-Poon I-V characteristics and the RF wide-band electric current gains change the Modulation of CE(Common-Emitter) amplifier description, and it had accomplished Current Gain Modulation by Ledge Bias that change in high frequency and wide bands. wide bands.s.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.307-307
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• 2014

정보화 시대로 접어들면서 동일한 공간에 더 많은 정보를 저장할 수 있고, 보다 빠른 동작이 가능한 비휘발성 메모리 소자에 대한 요구가 증가하고 있다. 하지만, 최근 비휘발성 메모리 소자 관련 연구보고에 따르면, 메모리 소자의 소형화 및 직접화 측면에서, 전하 저장을 기반으로 하는 기존의 Floating-Gate(FG) Flash 메모리는 20 nm 이하 공정에서 한계가 예측 되고 있다. 따라서, 이러한 FG Flash 메모리의 한계를 해결하기 위해, 기존에 FET 기반의 FG Flash 구조와 같은 3 terminal이 아닌, Diode와 같은 2 terminal로 동작이 가능한 ReRAM, PRAM, STT-MRAM, PoRAM 등 저항변화를 기반으로 하는 다양한 종류의 차세대 메모리 소자가 연구되고 있다. 그 중, 저항 변화 메모리(ReRAM)는 CMOS 공정 호환성, 3D 직접도, 낮은 소비전력과 빠른 동작 속도 등의 우수한 동작 특성을 가져 차세대 비휘발성 메모리로 주목을 받고 있다. 또한, 상하부 전극의 2 terminal 만으로 소자 구동이 가능하기 때문에 Passive Crossbar-Array(CBA)로 적용하여 플래시 메모리를 대체할 수 있는 유력한 차세대 메모리 소자이다. 하지만, 이를 현실화하기 위해서는 Passive CBA 구조에서 발생할 수 있는 Read Disturb 현상, 즉 Word-Line과 Bit-Line을 통해 선택된 소자를 제외하고 주변의 다른 소자를 통해 흐르는 Sneak Leakage Current(SLC)를 차단하여 소자의 메모리 State를 정확히 sensing하기 위한 연구가 선행 되어야 한다. 따라서, 현재 이러한 이슈를 해결하기 위해서, 많은 연구 그룹에서 Diodes, Threshold Switches와 같은 ReRAM에 Selector 소자를 추가하는 방법, 또는 Self-Rectifying 특성 및 CRS 특성을 보이는 ReRAM 구조를 제안 하여 SLC를 차단하고자 하는 연구가 시도 되고 있지만, 아직까지 기초연구 단계로서 아이디어에 대한 가능성 정도만 보고되고 있는 현실 이다. 이에 본 논문은 Passive CBA구조에서 발생하는 SLC를 해결하기 위한 새로운 아이디어로써, 본 연구 그룹에서 선행 연구로 확보된 안정적인 저항변화 물질인 SiN를 정류 특성을 가지는 n-Si/Ti 기반의 Schottky Diode와 결합함으로써 기존의 CBA 메모리의 Read 동작에서 발생하는 SLC를 차단 할 수 있는 1SD-1R 구조의 메모리 구조를 제작 하였으며, 본 연구 결과 기존에 문제가 되었던 SLC를 차단 할 수 있었다.

• Transactions on Electrical and Electronic Materials
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• v.18 no.4
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• pp.199-202
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• 2017

Silicon carbide (SiC) is being spotlighted as a next-generation power semiconductor material owing to the characteristic limitations of the existing silicon materials. SiC has a wider band gap, higher breakdown voltage, higher thermal conductivity, and higher saturation electron mobility than those of Si. When using this material to implement Schottky barrier diode (SBD) devices, SBD-state operation loss and switching loss can be greatly reduced as compared to that of traditional Si. However, actual SiC SBDs exhibit a lower dielectric breakdown voltage than the theoretical breakdown voltage that causes the electric field concentration, a phenomenon that occurs on the edge of the contact surface as in conventional power semiconductor devices. Therefore in order to obtain a high breakdown voltage, it is necessary to distribute the electric field concentration using the edge termination structure. In this paper, we designed an edge termination structure using a field plate structure through oxide etch angle control, and optimized the structure to obtain a high breakdown voltage. We designed the edge termination structure for a 650 V breakdown voltage using Sentaurus Workbench provided by IDEC. We conducted field plate experiments. under the following conditions: $15^{\circ}$, $30^{\circ}$, $45^{\circ}$, $60^{\circ}$, and $75^{\circ}$. The experimental results indicated that the oxide etch angle was $45^{\circ}$ when the breakdown voltage characteristics of the SiC SBD were optimized and a breakdown voltage of 681 V was obtained.