• The Journal of the Korea Contents Association
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• v.12 no.11
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• pp.20-29
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• 2012

Recently, Digital Information Display(DID) technologies have been used to advertise the various contents such as video, image, text and etc. However most of recent DIDs are still using the traditional one directional advertising mechanism delivering the contents only to the customers. In this paper, we present the design and implementation of an App Scheduler on Android platform to effectively manage the Android Apps related to the advertisement which can attract customers' attention and reflect their ideas in the advertisement.

• Journal of Intelligence and Information Systems
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• v.2 no.1
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• pp.75-91
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• 1996

제철소에서의 원료 운송 작업은, 선박에 선적된 원료를 하역하여 야드에 적치한 후, 제반 원료 소요공장까지의 벨트 컨베이어를 통한 원료 수송 작업을 의미한다. 본 연구에서는 원료 운송과 관련한 선박 접안, 원료 하역 및 벨트 컨베이어 수송 일정 계획을 효과적으로 수립하기 위하여 이단계 계획적 구조를 이용한 일정계획 휴리스틱을 개발하고 이를 구현하기 위한 전문가 시스템을 개발하였다. 이단계 계층적 구조는 상위 단계의 Scheduler 와 하위 단계의 복수개의 Dispatcher 로 구성되어 있다. 하위 단계의 Dispatcher는 주어진 제약조건하에서 단위 문제를 해결하고 이를 상위 단계의 Scheduler에게 보고하게 된다. 상위 단계의 Scheduler 는 전체적인 문제 해결의 우선 순위 결정 및 Dispatcher 간의 상층을 해결하는 역할을 맡게 된다. 이러한 계층적 구조를 이용한 분산처리를 통해 문제의 복잡성을 줄이고, 시스템 설계의 모듈화 및 유연성있는 시스템 구축이 가능하게 되었다. 본 시스템은 실시간 전문가 시스템 도구인 G2를 이용하여 SUN Workstation에서 개발되었다.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.6
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• pp.440-445
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• 2004

The design and implementation of a Network Processor using System-on-a-chip(SoC) technology is presented. The proposed network processor can handle several protocols as well as various types of traffics simultaneously. The proposed SoC consists of ARM processor core, ATM block, AAL processing block, Ethernet block and a scheduler. The scheduler guarantees QoS of the voice traffic and supports multiple AAL2 packet. The SoC is manufactured on the 0.35 micron fabrication line of HYNIX semiconductor, the total number of gates is about 312,000, for a maximum operating frequency of over to 50㎒.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.1 s.232
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• pp.96-106
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• 2005

An integrated single-wafer processing tool, composed of multiple single wafer processing modules, transfer robots, and load locks, has complex routing sequences, and often has critical post-processing residency constraints. Scheduling of these tools is an intricate problem, and testing schedulers with actual tools requires too much time and cost. The Single Wafer Processor (SWP) simulator presented in this paper is to validate an on-line scheduler, and evaluate performance of integrated single-wafer processing tools before the scheduler is actually deployed into real systems. The data transfer between the scheduler and the simulator is carried out with TCP/IP communication using messages and files. The developed simulator consists of six modules, i.e., GUI (Graphic User Interface), emulators, execution system, module managers, analyzer, and 3D animator. The overall framework is built using Microsoft Visual C++, and the animator is embodied using OpenGL API (Application Programming Interface).

• Journal of the Semiconductor & Display Technology
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• v.16 no.3
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• pp.25-30
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• 2017

Arago's disk system consists of a speed controller of the DC motor (inner loop controller) and a position controller of the magnetic bar angle (main controller), which are implemented by the design of the PI and PID controller, respectively. First, we analyzed the nonlinear characteristics of the Arago disk system and found the operating point range of three locations as a result. In this paper, a gain scheduler method was applied to guarantee a constant control performance in the range of $0{\sim}130^{\circ}C$, and a structure to change the controller according to the control reference value based on the previously obtained operating points was experimentally implemented. The Distributed Control Systems (DCS) configuration using the Controller Area Network (CAN) was used to verify the proposed method by improving the operational efficiency of the entire experimental system. So, simplicity of the circuit and easy diagnosis were achieved through a single CAN bus communication.

• Journal of the Korea Society of Computer and Information
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• v.24 no.4
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• pp.1-9
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• 2019

LRR(Loose Round Robin) warp scheduling policy for GPU architecture results in high warp-level parallelism and balanced loads across multiple warps. However, traditional LRR policy makes multiple warps execute long latency operations at the same time. In cases that no more warps to be issued under long latency, the throughput of GPUs may be degraded significantly. In this paper, we propose a new warp scheduling policy which utilizes latency hiding, leading to more utilized memory resources in high performance GPUs. The proposed warp scheduler prioritizes memory instruction based on GTO(Greedy Then Oldest) policy in order to provide reduced memory stalls. When no warps can execute memory instruction any more, the warp scheduler selects a warp for computation instruction by round robin manner. Furthermore, our proposed technique achieves high performance by using additional information about recently committed warps. According to our experimental results, our proposed technique improves GPU performance by 12.7% and 5.6% over LRR and GTO on average, respectively.

• The Journal of the Korea Contents Association
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• v.21 no.6
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• pp.12-18
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• 2021

A proportional share scheduler allocates CPU time to tasks and determines which task will be dispatched according to their priorities. In this paper, we investigate the correlation between the characteristics of applications and task priorities in the Linux Completely Fair Scheduler(CFS), which is one of the representative proportional share schedulers. We also propose a method of controlling the granularity of priority assignments according to the characteristics of applications. We implemented the proposed technique in a Linux system and confirmed the meaningful experimental results.

• Proceedings of the Korea Information Processing Society Conference
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• 2010.04a
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• pp.241-242
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• 2010

분산 Job Scheduling 문제에서 Makespan 은 항상 타 성능지표를 대표하는 단일 목표치 (Objective)가 되기 어려운 측면이 있다. 그러나 기존의 Job Scheduler 관련 제안들은 Makespan 만을 단일 목표치로 최적화 시킴으로써, 성능적 우수성을 입증하는 한계점이 있었다. 그러므로 본고에서는 Makespan 및 Throughput 을 동시에 최소화하여 개별 가중치로 정량화될 수 있는 다양한 성능 요구사항에 적합한 복수 대안 (Scheduling Alternatives)들을 제공할 수 있는 GA 기반 스케줄링 기법에 대해 제안한다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.48 no.8
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• pp.42-50
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• 2011

Recently, research activities on the future internet are being actively performed in foreign and domestic. In domestic, ETRI and 4 universities are focused on implementation of a testbed for research on the future internet named as 'FiRST(Future Internet Research for Sustainable Testbed)'. In the 'FiRST' project, 4 universities are performing a project in collaboration named as 'FiRST@PC' project that is for an implementation of the testbed using the programmable platform-based openflow switches. Currently, the research on the virtualization of the testbed is being performed that has a purpose for supporting an isolated network to individual researcher. In this paper, we implemented a traffic scheduler for providing QoS by using the programmable platform that performs a hardware-based packet processing and we are implemented a testbed using that traffic scheduler. We perform a performance evaluation of the traffic scheduler on the testbed. As a result, we show that the hardware-based NetFPGA scheduler can provide reliable and stable QoS to virtualized networks of the Future Internet Testbed.

• The KIPS Transactions:PartA
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• v.18A no.6
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• pp.255-264
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• 2011

A sensor network is a special network that makes physical data sensed by sensor nodes and manages the data. The sensor network is a technology that can apply to many parts of field. It is very important to transmit the data to a user at real-time. The core of the sensor network is a sensor node and small operating system that works in the node. TinyOS developed by UC Berkeley is a sensor network operating system that used many parts of field. It is event-driven and component-based operating system. Basically, it uses non-preemptive scheduler. If an urgent task needs to be executed right away while another task is running, the urgent one must wait until another one is finished. Because of that property, it is hard to guarantee real-time requirement in TinyOS. According to recent study, Priority Level Scheduler, which can let one task preempt another task, was proposed in order to have fast response in TinyOS. It has restrictively 5 priorities, so a higher priority task can preempt a lower priority task. Therefore, this paper suggests Preemptive EDF(Earliest Deadline First) Scheduler that guarantees a real-time requirement and reduces average respond time of user tasks in TinyOS.