• The Transactions of the Korean Institute of Electrical Engineers B
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• v.50 no.4
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• pp.188-200
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• 2001

This paper presents a technique for reconstructing converter line currents using the information from a single current sensor in the DC-link for voltage-source PWM converters. When three-Phase input currents cannot be reconstructed, three methods to acquire the input current are compared. Two of them are methods of modifying the switching state (I, II), another is a method of using the predictive state observer. Also, compensation of sampling delay, and a simultaneous sample value of input currents in the center of a switching period are included. Suitable criteria for the comparison are identified, and the differences in the performance of these methods are investigated through experimental results for a typical V-S PWM converter rated at 10kVA.

• Proceedings of the Korean Institute of Building Construction Conference
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• 2011.05a
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• pp.211-212
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• 2011

The construction industry has become larger and higher in size. The process of high-rise building construction is complicated and has various conditions affecting productivity. Analysing productivity in high-rise buildings is difficult despite the various productivity analysis methods. In this study, data was collected from actual construction site to analyse the productivity of curtain wall operation by means of Work sampling and Method Productivity Delay Model. As a result, this paper suggests advantages and disadvantages deducted from comparing the two productivity analysis methods.

• Journal of Power Electronics
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• v.11 no.4
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• pp.583-590
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• 2011

Three-level NPC inverters have been put into practical use for years especially in high voltage high power grids. This paper researches three-level active power filters (APFs). In this paper a mathematical model in the d-q coordinates is presented for 3-phase 3-wire NPC APFs. The deadbeat control scheme is obtained by using state equations. Canceling the delay of one sampling period and providing the predictive value of the harmonic current is a key problem of the deadbeat control. Based on this deadbeat control, the predictive output current value is obtained by the state observer. The delay of one sampling period is remedied in this digital control system by the state observer. The predictive harmonic command current value is obtained by the repetitive predictor synchronously. The repetitive predictor can achieve a better prediction of the harmonic current with the same sampling frequency, thus improving the overall performance of the system. The experiment results indicate that the steady-state accuracy and the dynamic response are both satisfying when the proposed control scheme is implemented.

• The Transactions of the Korean Institute of Power Electronics
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• v.21 no.2
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• pp.168-174
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• 2016

In this paper, current control using PI controller in the synchronous reference frame is analyzed through the relationship among bandwidth, resonance frequency, and sampling frequency in the grid-connected inverter with LCL filter. Stability is investigated by using bode plot in frequency domain and root locus in discrete domain. The feedback variable is the grid current, which is regulated by the PI controller in the synchronous reference frame. System delay is modeled as 1.5Ts, which contains computational and PWM modulator delay. Two resonance frequencies are given at 815 Hz and 3.16 kHz from LCL filter parameters. Sufficient phase and gain margins can be obtained to guarantee stable current control, in case that resonance frequency is above one-sixth of the sampling frequency. Unstable current control is performed when resonance frequency is below one-sixth of the sampling frequency. Analysis results of stability from frequency response and discrete response is the same regardless of resonance frequency. Finally, stability of current control based on theoretical analysis is clearly verified through simulation and experiment in grid-connected inverters with LCL filter.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.2
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• pp.17-25
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• 2012

A general discretization method for input-driven nonlinear continuous time-delay systems is proposed, which can be applied to general order sampling hold assumptions. It is based on a combination of Taylor series expansion and the theories of sampling and hold. The mathematical structure of the new discretization scheme is introduced in detail. The performance of the proposed discretization procedure is evaluated by two degrees of systems. The results show that the proposed scheme is applicable to control systems.

• Journal of Mechanical Science and Technology
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• v.15 no.1
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• pp.1-9
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• 2001

The recent spread of scaled telemanipulation into microsurgery and the nano-world increasingly requires the identification of the possible operation region as a main system specification. A teleoperation system is a complex cascaded system since the human operator, master, slave, and communication are involved bilaterally. Hence, a small time delay inside a master and slave system can be critical to the overall system stability even without communication time delay. In this paper we derive an upper bound of the scaling product of position and force by using Llewellyns unconditional stability. This bound can be used for checking the validity of the designed bilateral controller. Time delay from the sample and hold of computer control and its effects on stability of scaled teleoperation are modeled and simulated based on the transfer function of the teleoperation system. The feasible operation region in terms of position and force scaling decreases sharply as the sampling rate decreases and time delays inside the master and slave increase.

• Journal of the Institute of Convergence Signal Processing
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• v.10 no.2
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• pp.127-131
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• 2009

In the digital waveguide theory, traveling waves are represented by general solution to the wave equation that is second-order linear partial differential equation. The movement of these waves can be implemented using only delay lines. An unit delay in the general digital waveguide describes a sampling time interval. However, in the space-based digital waveguide the unit delay implies the spatial sampling distance. In consideration of these differences between two models, it is known that the space-based digital waveguide model is adequate to synthesize pitch-shifted sounds such as vibrato because the propagation distance can be directly control. In this paper, the time-based digital waveguide model which also synthesizes pitch-shifted sounds is proposed and compared with space-based digital waveguide.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.8
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• pp.1805-1812
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• 2011

Bandpass sampling technique has an advantage that it uses lower sampling frequency than Nyquist criterion. But special care is required in choosing sampling frequency to avoid self-image overlapping in the first Nyquist region. Recently, the second-order BPS techniques which can suppress possible self-image by using an additional ADC and by employing digital signal processing have been proposed. This paper addresses a complex BPS based SDR front-end. Unlike general second-order BPS, it needs simple FIR filter to compensate delay in the second ADC. We show a method to find proper sampling frequencies to down convert RF signals selected by tunable RF filter operating in arbitrary frequency range.

• Journal of Power Electronics
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• v.13 no.3
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• pp.349-361
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• 2013

As a result of the advantages such as high efficiency, continuous current and high stability margin, push-pull converter with continuous current (PPCWCC) is competitive for battery discharge regulator (BDR) which plays an important role in power conditioning unit (PCU). Leakage inductance yields current spike in low-ripple current of PPCWCCs. The operating modes are added due to leakage inductance. Therefore the steady state performance is affected, which is embodied in the spike of low-ripple current. PPCWCCs which are suitable for BDR can be separated into three types by current spike characteristics. Three representative topologies IIs1, IIcb2 and Is3 are analyzed in order to investigate the factors on the magnitude and duration of spike. Equivalent current sampling method (ECSM) which eliminates the sampling time delay and achieves excellent dynamic performance is adopted to prevent the spike disturbance on current sampling. However, ECSM reduces the sampling accuracy and telemetry accuracy due to neglecting the spike. In this paper, ECSM used in PPCWCCs is summarized. The current sampling error is analyzed in quality and quantity, which provides the foundation for offsetting and enhancing the telemetry accuracy. Finally, current sampling error rate of three topologies is compared by experiment results, which verify the theoretical analysis.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.411-424
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• 2017

An all-digital delay-locked loop (DLL) for a mobile memory interface, which runs at 0.11-2.5 GHz with a phase-shift capability of $180^{\circ}$, has two internal DLLs: a global DLL which uses a time-to-digital converter to assist fast locking, and shuts down after locking to save power; and a local DLL which uses a phase detector with an adaptive phase sampling window (WPD) to reduce jitter accumulation. The WPD in the local DLL adjusts the width of its sampling window adaptively to control the loop bandwidth, thus reducing jitter induced by UP/DN dithering, input clock jitter, and supply/ground noise. Implemented in a 65 nm CMOS process, the DLL operates over 0.11-2.5 GHz. It locks within 6 clock cycles at 0.11 GHz, and within 17 clock cycles at 2.5 GHz. At 2.5 GHz, the integrated jitter is $954fs_{rms}$, and the long-term jitter is $2.33ps_{rms}/23.10ps_{pp}$. The ratio of the RMS jitter at the output to that at the input is about 1.17 at 2.5 GHz, when the sampling window of the WPD is being adjusted adaptively. The DLL consumes 1.77 mW/GHz and occupies $0.075mm^2$.