• 전자공학회논문지
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• 제52권9호
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• pp.21-27
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• 2015

High resistivity(HR) silicon-on-insulator(SOI) RF CMOS 공정 인덕터의 모델 파라미터를 정확히 결정하기 위하여 직접추출과 simultaneous optimization을 사용한 개선된 방법을 개발하였다. 먼저, 대칭형 인덕터와 센터탭이 접지된 대칭형 인덕터 등가회로들의 Y 및 Z-파라미터 방정식 유도를 통해 일부 모델 파라미터들을 직접 추출하고, 병렬 저항과 전체 인덕턴스 방정식들로 미지 변수들을 줄여 모델링 정확도를 향상시켰다. 또한, 두 등가회로의 동일한 모델 파라미터들을 공통 변수로 두고 S-파라미터 데이터 세트를 동시에 optimization함으로써 optimization 정확도를 크게 향상시켰다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.35-35
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• 2009

Capacitorless one transistor dynamic random access memory (1T-DRAM) cells were fabricated on the fully depleted strained-silicon-on-insulator (FD sSOI) and the effects of silicon back interface state on buried oxide (BOX) layer on the memory properties were evaluated. As a result, the fabricated 1T-DRAM cells showed superior electrical characteristics and a large sensing current margin (${\Delta}I_s$) between "1" state and "0" state. The back interface of SOI based capacitorless 1T-DRAM memory cell plays an important role on the memory performance. As the back interface properties were degraded by increase rapid thermal annealing (RTA) process, the performance of 1T-DRAM was also degraded. On the other hand, the properties of back interface and the performance of 1T-DRAM were considerably improved by post RTA annealing process at $450^{\circ}C$ for 30 min in a 2% $H_2/N_2$ ambient.

• 한국정보통신학회논문지
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• 제11권10호
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• pp.1910-1915
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• 2007

본 논문에서는 NQS(non-quasi-static)효과를 고려한 FD(fully depleted)-SOI(silicon-on-insulator) MOSFETs의 고주파 소신호 모델링을 위한 등가회로 변수들을 간단하고 정확히 추출하는 방법을 제시하였다. 제시된 추출방법은 임피던스와 어드미턴스 행렬계산으로 S-파라미터의 측정 결과로부터 MOSFET의 외부 기생용량과 기생저항을 제거하여 물리적인 특성을 바탕으로 한 MOSFET의 내부등가회로변수가 간단히 추출되어진다. 제시된 방법으로 등가 회로를 구한 후 Y-파라미터를 계산하여 측정치와 비교한 결과 500MHz부터 200Hz까지 잘 일치함을 확인하였다.

• Biotechnology and Bioprocess Engineering:BBE
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• 제11권6호
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• pp.530-537
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• 2006

Recently isolated, Pseudomonas putida SN1 grows on styrene as its sole carbon and energy source through successive oxidation of styrene by styrene monooxygenase (SMO), styrene oxide isomerase (SOI), and phenylacetaldehyde dehydrogenase. For the production of (S)-styrene oxide, two knockout mutants of SN1 were constructed, one lacking SOI and another lacking both SMO and SOI. These mutants were developed into whole-cell biocatalysts by transformation with a multicopy plasmid vector containing SMO genes (styAB) of the SN1. Neither of these self-cloned recombinants could grow on styrene, but both converted styrene into an enantiopure (S)-styrene oxide (e.e. > 99%). Whole-cell SMO activity was higher in the recombinant constructed from the SOI-deleted mutant (130 U/g cdw) than in the other one (35 U/g cdw). However, the SMO activity of the former was about the same as that of the SOI-deleted SN1 possessing a single copy of the styAB gene that was used as host. This indicates that the copy number of styAB genes is not rate-limiting on SMO catalysis by whole-cell SN1.

• 전자공학회논문지A
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• 제29A권11호
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• pp.91-96
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• 1992

The technology of LOCOS(LOCal Oxidation of Silicon) was used to form the island of SOI film. After this, the SOI film was recrystallized by CO$_2$ laser and metal gate nMOSFETs were fabricated on this SOI film and their electrical characteristics were measured. The kink effect was not nearly observed and edge channel effect was found in the SOI nMOSFETs. The threshold voltage was about 0.5V, the electron mobility was about 340cm$^2$V$\cdot$S and an ON/OFF ratio above 10$^{5}$ was obtained at V_{DS}$=4V. The electrical characteristics were improved by laser recrystallization.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.473-481
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• 2012

For a mesa-isolated small geometry SOI MOSFET, the potentials in the silicon film, front, back, and side-wall oxide layers can be derived three-dimensionally. Using Taylor's series expansions of the trigonometric functions, the derived potentials are written in terms of the natural length that can be determined by using the derived formula. From the derived 3-D potentials, the minimum values of the front and the back surface potentials are derived and used to obtain the closed-form expressions for the front and back gate threshold voltages as functions of various device parameters and applied bias voltages. Obtained results can be found to explain the drain-induced threshold voltage roll-off and the narrow width effect of a fully depleted small geometry SOI MOSFET in a unified manner.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 추계학술대회 논문집 학회본부
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• pp.367-369
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• 1995

An SOI LDMOS(Silicon-On-Insulator Lateral Double diffused MOSPET) with a tapered field plate is proposed and investigated in terms of the breakdown voltage and on-resistance using 2-D simulator, MEDICI. The results of conventional SOI LDMOS with a stepped field plate are reported for the comparison. Simulated breakdown voltage of the proposed LDMOS is found to be higher than that of conventional LDMOS since surface electric field can be reduced due to the field plate over the tapered oxide. On-resistance of proposed LDMOS is found to be lower than that of conventional LDMOS by 10%.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권9호
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• pp.605-610
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• 1999

An SOI(Silicon-On-Insulator) LD(Lateral Double-diffused)MOS with a recessed source structure is proposed to improve the on-resistance and the breakdown voltage. The recessed source structure can decrease the on-resistance by reducing the path of electron current, also increase the breakdown voltage by extending the effective length of gate field plate. Simulation results by TSUPREM4 and MEDICI have shown that the on-resistance of the LDMOS with a recessed source was 26% lower than conventional LDMOS. The breakdown voltage of proposed device was found to be 45V while that of conventional device was 36.5 V. At the same breakdown voltage of 36.5V, the on-resistance of the LDMOS with a recessed source was 41% lower than that of conventional structure.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.264-275
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• 2008

Electron mobility has been investigated theoretically in undoped double-gate (DG) MOSFETs of different channel architectures: a relaxed-Si DG SOI, a strained-Si (sSi) DG SSOI (strained-Si-on-insulator, containing no SiGe layer), and a strained-Si DG SGOI (strained-Si-on-SiGe-on-insulator, containing a SiGe layer) at 300K. Electron mobility in the DG SSOI device exhibits high enhancement relative to the DG SOI. In the DG SGOI devices the mobility is strongly suppressed by the confinement of electrons in much narrower strained-Si layers, as well as by the alloy scattering within the SiGe layer. As a consequence, in the DG SGOI devices with thinnest strained-Si layers the electron mobility may drop below the level of the relaxed DG SOI and the mobility enhancement expected from the strained-Si devices may be lost.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.354-355
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• 2008

The sensitivity and sensing margin of SOI(silicon on insulator) nano-wire BioFET(field effect transistor) were investigated by using back-gate bias. The channel conductance modulation was affected by doping concentration, channel length and channel width. In order to obtain high sensitivity and large sensing margin, low doping concentration, long channel and narrow width are required. We confirmed that the electrical sensing by back-gate bias is effective method for evaluation and optimization of bio-sensor.