• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1564-1574
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• 1999

In order to improve the efficiency of optimizing compilers, integration of register allocation and instruction scheduling has been extensively studied. One of the promising integration techniques is register allocation based on register-reuse chains. However, the generation of register-reuse chains in the previous approach was not completely systematic and consequently it creates unnecessarily dependencies that restrict instruction scheduling. This paper proposes a new register allocation technique based on a systematic generation of register-reuse chains. The first phase of the proposed technique is to generate register-reuse chains that are optimal in the sense that no additional dependencies are created. Thus, register allocation can be done without restricting instruction scheduling. For the case when the optimal register-reuse chains require more than available registers, the second phase reduces the number of required registers by merging the register-reuse chains. Chain merging always generates additional dependencies and consequently enforces the execution order of instructions. A heuristic is developed for the second phase in order to reduce additional dependencies created by merging chains. For matrix multiplication program, the number of registers resulting from the first phase is small enough to fit into available registers for most basic blocks. In addition, it is shown that the restriction to instruction scheduling is reduced by the proposed merging heuristic of the second phase.

• Journal of Computing Science and Engineering
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• v.5 no.2
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• pp.121-130
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• 2011

Recent research indicates that transient errors will increasingly become a critical concern in microprocessor design. As embedded processors are widely used in reliability-critical or noisy environments, it is necessary to develop cost-effective fault-tolerant techniques to protect processors against transient errors. The register file is one of the critical components that can significantly affect microprocessor system reliability, since registers are typically accessed very frequently, and transient errors in registers can be easily propagated to functional units or the memory system, leading to silent data error (SDC) or system crash. This paper focuses on investigating the impact of register file soft errors on system reliability and developing cost-effective techniques to improve the register file immunity to soft errors. This paper proposes the register vulnerability factor (RVF) concept to characterize the probability that register transient errors can escape the register file and thus potentially affect system reliability. We propose an approach to compute the RVF based on register access patterns. In this paper, we also propose two compiler-directed techniques and a hybrid approach to improve register file reliability cost-effectively by lowering the RVF value. Our experiments indicate that on average, RVF can be reduced to 9.1% and 9.5% by the hyperblock-based instruction re-scheduling and the reliability-oriented register assignment respectively, which can potentially lower the reliability cost significantly, without sacrificing the register value integrity.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.11
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• pp.987-992
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• 2014

Register control of roll-to-roll printing system for printed electronics requires accurate measurement of register errors. The register marks used for the recognition of patterns position between layers have inherently defects due to low printability of register marks themselves, which brings out inaccurate register accuracy and consequently low performance of printed electronics devices. In this study, the compensation methods for the unrecognized or missing register data are proposed to improve the recognition and consequently the control performance of register accuracy in roll-to-roll printing equipment. The compensation methods using the prior data and the linear interpolation are proposed and compared with the case without compensation for the simulation as well as experiment. Only the linear interpolation method could successfully compensate the missing data and consequently improve the register control performance. We should apply the compensation process of the register errors to improve the register control accuracy in the roll-to-roll printing equipment.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.8
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• pp.1211-1220
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• 1990

This paper describes and implements a design method of register allocation as a required module of RISC compiler systems. It compiles a C program to a machine-independent intermediate language, translates each variable into symbolic register. After local allocation process for the symbolic registers, global register allocation is executed by applying the graph coloring algorithm. This register allocation phase is designed for a system with the large register file like RISC machines.

• Journal of Korean Port Research
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• v.11 no.1
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• pp.129-137
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• 1997

The traditional approaches to determine the flag of convenience and second register of flagging-out in Korea international ship register and investigater and weakness of those approaches are revealed. A realistic approach to determine the paper company of shipping and sub-standard vessel of shipbuilding is suggested by introducing register factors obtained from Norwegian and Denish international ship register experiment for the new register.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.323-324
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• 2006

This paper presents dynamics of register error on a compensator roll type converting machine. Though a register control is an important aspect of a converting machine, it has not been taken into account as a main subject. Lately, demands for high speed converting machines over 500mpm(m/min) are raising but domestic converting industries can not come up with the high speed machines because capacities fur designing of the converting machine is restricted lower than 300mpm. Moreover register control is the key to product flexible displays through roll-to-roll systems. In this paper, a compensator roll type register controller is analyzed using mathematical model of register error. A case study for reducing transient register errors is discussed.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.325-326
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• 2006

Recently, it is concentrated on productivity improvement in high speed operation by converting industries. Register error is becoming the one of the most issued problem. Moreover register control is the key to product flexible displays through roll-to-roll systems. This paper presents a derivation of register error modeling. And the dynamics of register error is simulated under various conditions. Register error is affected by both roll velocity and tension between the front and back span. And dynamics of register error is to be an interaction in succeeding spans.

• Proceedings of the IEEK Conference
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• 2000.07b
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• pp.953-956
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• 2000

Application specific DSPs often employ irregular datapath structures with distributed registers. In the scheduling phase of retargetable compilation, resolution of register usage conflicts comes to be a new constraint for such datapaths. This paper presents a method of register constraint analysis which attempts to minimize the number of the spill codes required for resolving the register usage conflicts. It searches for a set of ordering restrictions among operations which sequentialize the lifetimes of the values residing in the same register as much as possible and thus minimize the number of the register conflict. Experimental results show that a combination of the proposed register constraint, analysis and list-based scheduling reduces the number of the register spills into 25%.

• Journal of Korean Library and Information Science Society
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• v.20
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• pp.241-284
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• 1993

Through the restoration, we can find that the register of houses, inhabitants and their ancestry, which is in the Sunsung Kim family registers, was fundamentally the census register of Kim Roe including more ancestry transformed into the lists of house, inhabitants and their ancestry of Kim Roe, Kim Bang-Seek, Kim Sung-Sae and Kim Hee-Bo. And we can find also the original forms were considerably damaged. That is, in the course of transformation, considerable parts of the contents of ancestry were not needed, so they were removed, the recordings of brotherandsisters, sons and their servants were also removed. By comparing of the restored census register of Kim Roe and the Sunsung Kim family registers, we can know the fact that when they published the family registers, the contents of the founder to the ninth descendants were totally depended on the census register of Kim Roe. The Census Register of King Taejo of Choson Dynasty(National Treasure No. 131) which has been recorded almost same periods as the census register of Kim Roe was remained as an original state. Therefore, it was greatly helpful for restoring the census register of Kim Roe. There were few materials which we can know the way of ordinary life in Koryo period. But through the census register of Kim Roe and the census Register of King Taejo of Choson Dynasty, we have a glimpse of their life history. Nevertheless we can find some demerits in the census register of Kim Roe as followers : First, it is not an original but a transformed one, while the Census Register of King Taejo of Choson Dynasty is first materials. Second, it was recorded the only one family. Finally, it was omitted the parts of his brotherandsisters, children and servants who lived with their master. According to these demerits its worth of materials for history will be descended more or less. Therefore, when we use this material, we should treat it more considerably.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.1 s.307
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• pp.1-8
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• 2006

This thesis proposes Arithmetic Shift Register(ASR) which can be used as pseudo random number generator. Arithmetic Shift. Register is defined as progression that multiplies random number D , not 0 or 1 at initial value which is not 0, and it is represented as ASR-D in this thesis. Irreducible polynomial that t which makes $'D^k=1'$ satisfies uniquely as $'t=2^n-1'$ over. $GF(2^n)$ is the characteristic polynomial of ASR-D , and the cycle of Arithmetic Shift Register has maximum cycle as $'2^n-1'$. Galois Linear Feedback Shift Register corresponds to ASR-2-1. Therefore, Arithmetic Shift Register proposed in this thesis generalizes Galois Linear Feedback Shift Register. Linear complexity of ASR-D over$GF(2^n)$ is $'n{\leq}LC{\leq}\frac{n^2+n}{2}'$ and in comparison with existing Linear Feedback Shift Register stability is high. The Software embodiment of arithmetic shift register proposed in this thesis is efficient than that of existing Linear Shift Register and hardware complexity is equal. Arithmetic shift register proposed in this thesis can be used widely in various fields such as cipher, error correcting codes, Monte Carlo integral, and data communication etc along with existing linear shift register.