• Korean Journal of Computational Design and Engineering
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• v.1 no.1
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• pp.33-44
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• 1996

This study deals with the development of wire path searching module as a part of automobile wire harness design system. Wire path searching module manages the free space, finds transition locations, and creates bundle paths to dramatically reduce a tedious iterative routing process which results in easy optimization of the bundle paths. A prime policy in the system configuration is to compromise between man's and computer's ability, and make it possible a designer's leading role in designing process. Human input is indispensable to cope with the special cases which were not considered in the initial design stage of the system. In this study, we improve the previous shortest-path-finding algorithm, (VGraph and RCA method) into a new method called Extended RCA. Bundles, connectors and transitions are handled as objects so one can manage and modify physical properties of the objects easily. Therefore a verification is allowed at any desired stage of design. The reuse of previous result is facilitated by using Dependency Structure, which represents the mutual relations among connectors, transitions, and bundles. Dependency Structure makes it possible the elimination of redundant calculating process, and consequently shorter routing time.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.37 no.7
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• pp.498-509
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• 1988

A BF(breadth-first) linear quadtree as a new data structure for image data is suggested, which enables us to compress the image data efficiently and to make operations of the compressed data easily. It is a list of path names for black nodes as the linear quadtree is. The path name for each black node of a BF linear quadtree is represented as a sequence of path codes from the root node to itself, whereas that of linear quadtree as a sequence of path codes from the root node to itself and fill characters for cut-offed path from it to any n-level node which corresponds to a pixel of an image. The BF linear quadtree provides a more efficent compression ratio than the linear quadtree does, because the former does not require redundant characters, fill characters, for the cut-offed paths. Several operations for image processing can be also implemented on this hierarchical structure efficiently, because it is composed of only the black nodes ad the linear quadtree is . In this paper, algorithms for several operations on the BF linear quadtree are defined and analyzed. Experimental results for forur image data are also given and discussed.

• Proceedings of the Korea Inteligent Information System Society Conference
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• 2001.01a
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• pp.30-33
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• 2001

The number of hidden neurons of the feed-forward neural networks is generally decided on the basis of experience. The method usually results in the lack or redundancy of hidden neurons, and causes the shortage of capacity for storing information of learning overmuch. This research proposes a new method for optimizing the number of hidden neurons bases on information entropy, Firstly, an initial neural network with enough hidden neurons should be trained by a set of training samples. Second, the activation values of hidden neurons should be calculated by inputting the training samples that can be identified correctly by the trained neural network. Third, all kinds of partitions should be tried and its information gain should be calculated, and then a decision-tree correctly dividing the whole sample space can be constructed. Finally, the important and related hidden neurons that are included in the tree can be found by searching the whole tree, and other redundant hidden neurons can be deleted. Thus, the number of hidden neurons can be decided. In the case of building a neural network with the best number of hidden units for tea quality evaluation, the proposed method is applied. And the result shows that the method is effective

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.2
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• pp.124-131
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• 1989

This paper showed that the system reliability optimization problem with sereval failure modes at each subsystem can be treated as efficient computational algorithm proposed here. This algorithm was developed by considering a generalized upper bounding which always exists in constraints when the system reliability optimization problem may be reformulated as 0-1 integer programming problem. We demonstrated the optimal allocation of redundant units for system reliability by using the proposed algorithm. Our algorithm is superior to others in terms of number of iterations and variables used.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.8
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• pp.1231-1239
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• 2015

We developed a robot that has four limbs, each of which has the same kinematic structure and has 6 degrees of freedom. The robot is 600mm high and weighs 4.3kg. The robot can perform walking and manipulating task by using the four limbs selectively. The robot has three walking patterns. The first one is biped walking, which uses two rear limbs as legs and two front limbs as arms. The second one is biped walking with supporting arms, which is basically biped walking but uses two arms as supporting legs for increasing stability of the robot. The last one is quadruped walking, which uses all the four limbs as legs. When a task for the robot is given, the robot approaches the task point by selecting an appropriate walking pattern among three walking patterns and performs the task. The robot has many degrees of freedom and is a redundant system for a three dimensional task. We propose a redundancy resolution method, in which the robot’s translational move to the task point is modeled as a prismatic joint and optimal solutions are obtained by optimizing some performance criteria. Several simulations are performed for the validity of the proposed method.

• Journal of the Korea Safety Management & Science
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• v.13 no.3
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• pp.45-53
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• 2011

The research proposes seven elimination rules of redundant gates and blocks in Fault Tree Analysis (FTA) and Reliability Block Diagram (RBD). The computational complexity of cut sets and path sets is NP-hard. In order to reduce the complexity of Minimal Cut Set (MCS) and Minimal Path Set (MPS), the paper classifies generation algorithms. Moreover, the study develops six implementation steps which reflect structural importance (SI) and reliability importance (RI) from Reliability Centered Maintenance (RCM) that a priority of using the functional logic among components is to reduce (improve) the system unavailability (or availability). The proposed steps include efficient generation of state structure function by Rare Event Enumeration (REA). Effective use of importance measures, such as SI and ill measures, is presented based on the number and the size of MCS and MPS which is generated from the reference[5] of this paper. In addition, numerical examples are presented for practitioners to obtain the comprehensive understanding of six steps that is proposed in this research.

• Journal of the Korean Society of Systems Engineering
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• v.18 no.2
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• pp.1-10
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• 2022

In general, similar or previous projects are mainly referred to in order to derive operational test and evaluation(OT&E) items after acquiring weapon system. The idea that a more systematic method is needed is spreading because some of OT&E items derived in this process are redundant or unnecessary. Therefore, in this topic, we plan to use WBS, a tool that classifies components into a hierarchical structure and manages development easily to achieve the weapon system development goal. In addition, the WBS tool is applied to the medium-sized standard vehicle project, which is currently being research and developed, to effectively derive OT&E items. As a result of deriving OT&E items by applying WBS to the vehicle development field and electric devices of the medium-sized standard vehicle project, the operability and relationship were judged early, and then contents of the evaluation items could be written substantially while working on environmental adaptability. In the future, it is judged that the efficiency will be increased if the method discussed in this paper is applied when deriving the OT&E items from the R&D development project.

• Annual Conference of KIPS
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• 2008.11a
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• pp.332-335
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• 2008

In this paper, based on H-tree, which is proposed as the basic data cube structure for multi-dimensional data stream analysis, we have done some analysis. We find there are a lot of redundant nodes in H-tree, and the tree-build method can be improved for saving not only memory, but also time used for inserting tuples. Also, to facilitate more fast and large amount of data stream analysis, which is very important for stream research, H^*-tree is designed and developed. Our performance study compare the proposed H^*-tree and H-tree, identify that H^*-tree can save more memory and time during inserting data stream tuples.

• Journal of the Korean Society for information Management
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• v.9 no.2
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• pp.20-42
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• 1992

MARC format for bibliographic data is to make the functions of shared cataloging easier and to provide exhaustivity for storing national bibliographic information, and powerful and flexible structure to communicate with international cataloging information. KORMARC format was developed in 1984 to form the basis for storing bibliographic information in a consistent and non-redundant form, and for sharing that information and manupulating it by computer. MARC format needs evolution to make the format more consistent and more useful, and to support new forms of material and new forms of control. The purpose of this study is to evaluate and discuss the original KORMARC format for monographs developed by the National Central Library in 1984 in order to provide the basis for a new revised format and format integration.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.1
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• pp.51-58
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• 2015

This paper proposes a 10-b SAR ADC. To increase the conversion speed and reduce the power consumption and area, redundant cycles were implemented digitally in a capacitor DAC. The capacitor DAC algorithm was straightforward switching, which included digital error correction steps. A prototype ADC was implemented in CMOS $0.18-{\mu}m$ technology. This structure consumed $140{\mu}W$ and achieved 59.4-dB SNDR at 1.25MS/s under a 1.8-V supply. The figure of merit (FOM) was 140fJ/conversion-step.