IEIE Transactions on Smart Processing and Computing

The Institute of Electronics and Information Engineers (대한전자공학회)
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Digital Error Correction for a 10-Bit Straightforward SAR ADC

  • Rikan, Behnam Samadpoor (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Abbasizadeh, Hamed (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Do, Sung-Han (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, Dong-Soo (College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Lee, Kang-Yoon (College of Information and Communication Engineering, Sungkyunkwan University)
  • Received : 2014.04.05
  • Accepted : 2014.11.19
  • Published : 2015.02.28
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Abstract

This paper proposes a 10-b SAR ADC. To increase the conversion speed and reduce the power consumption and area, redundant cycles were implemented digitally in a capacitor DAC. The capacitor DAC algorithm was straightforward switching, which included digital error correction steps. A prototype ADC was implemented in CMOS $0.18-{\mu}m$ technology. This structure consumed $140{\mu}W$ and achieved 59.4-dB SNDR at 1.25MS/s under a 1.8-V supply. The figure of merit (FOM) was 140fJ/conversion-step.

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References

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