References
- Ba Ro Saim Sung, Sang-Hyun Cho, Chang-Kyo Lee, Jong-In Kim, and Seung-Tak Ryu "A Time-Interleaved Flash-SAR Architecture for High Speed A/D Conversion." ISCAS 2009
- Ba Ro Saim Sung, Chang-Kyo Lee, Wan Kim, Jong-In Kim, Hyeok-Ki Hong, Ghil-geun Oh, Choong-Hoon Lee, Michael Choi, Ho-Jin Park, and Seung-Tak Ryu "A 6 bit 2 GS/s Flash-Assisted Time-Interleaved (FATI) SAR ADC with Background Offset Calibration." ASSCC 2013
- Lu Sun, Yuxiao Lu and Tingting Mo "A 300MHz 10b Time-Interleaved Pipelined-SAR ADC.", CARFIC 2013
- Binhee Kim, Long Yan, Jerald Yoo, Namjun Cho, and Hoi-Jun Yoo "An Energy-Efficient Dual Sampling SAR ADC with Reduced Capacitive DAC." ISCAS 2009
- Song Lan, Chao Yuan, Yvonne Y.H.Lam and Liter Siek "An Ultra Low-Power Rail-to-Rail Comparator for ADC Designs.", MWSCAS 2011