• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.341-342
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• 2007

The IRFPA (InfraRed Focal Plane Array) ROIC (ReadOut Integrated Circuit) was designed in folded-cascode Op-Amp using $0.35{\mu}m$ CMOS technology. As the folded-cascode has high open-loop voltage gain and fast settling time, that used in many analog circuit designs. In this paper, folded-cascode Op-Amp for ROIC of the $32{\times}32$ IRFPA has been designed. HSPICE simulation results are unit gain bandwidth of 13.0MHz, 90.6 dB open loop gain, 8 V/${\mu}m$ slew rate, 600 ns settling time and $66^{\circ}$ phase margin.

• Journal of Sensor Science and Technology
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• v.32 no.2
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• pp.105-109
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• 2023

In this study, we present a power-efficient driving method for gas sensor systems based on the analysis of input signal characteristics. The analysis of the gas sensor output signal characteristics in the frequency domain shows that most of the signal portions are distributed in a relatively low frequency region when extracting the gas sensor signal, which can lead to further performance improvement of the gas sensor system. Therefore, the proposed gas signal extracting technique changes the operating frequency of the read-out circuit based on the frequency characteristics of the output signal of the gas sensor, resulting in a reduction of power consumption at the whole system level. The proposed sensing technique, which can be applied to a general-purpose commercial gas sensor system, was implemented in a printed circuit board (PCB) to verify its effectiveness at the commercial level.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.8
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• pp.1868-1876
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• 2010

In this paper, we design a 256-bit EEPROM IP using only logic process-based devices. We propose EEPROM core circuits, a control gate (CG) and a tunnel gate (TG) driving circuit, to limit the voltages between the devices within 5.5V; and we propose DC-DC converters : VPP (=+4.75V), VNN (-4.75V), and VNNL (=VNN/3) generation circuit. In addition, we propose switching powers, CG_HV, CG_LV, TG_HV, TG_LV, VNNL_CG, VNNL_TG switching circuit, to be supplied for the CG and TG driving circuit. Simulation results under the typical simulation condition show that the power consumptions in the read, erase, and program mode are $12.86{\mu}W$, $22.52{\mu}W$, and $22.58{\mu}W$ respectively. Furthermore, the manufactured test chip operated normally and generated its target voltages of VPP, VNN, and VNNL as 4.69V, -4.74V, and -1.89V.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.509-518
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• 2023

In this paper, we designed a 4Kb poly-fuse OTP IP (Intellectual Property) required for analog circuit trimming and calibration. In order to reduce the BL resistance of the poly-fuse OTP cell, which consists of an NMOS select transistor and a poly-fuse link, the BL stacked metal 2 and metal 3. In order to reduce BL routing resistance, the 4Kb cells are divided into two sub-block cell arrays of 64 rows × 32 rows, with the BL drive circuit located between the two 2Kb sub-block cell arrays, which are split into top and bottom. On the other hand, in this paper, we propose a core circuit for an OTP cell that uses one poly-fuse link to one select transistor. In addition, in the early stages of OTP IP development, we proposed a data sensing circuit that considers the case where the resistance of the unprogrammed poly-fuse can be up to 5kΩ. It also reduces the current flowing through an unprogrammed poly-fuse link in read mode to 138㎂ or less. The poly-fuse OTP cell size designed with DB HiTek 90nm CMOS process is 11.43㎛ × 2.88㎛ (=32.9184㎛2), and the 4Kb poly-fuse OTP IP size is 432.442㎛ × 524.6㎛ (=0.227mm²).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.5
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• pp.529-538
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• 1992

Recently, image signal processing techniques for HDTV signal have been drastically developed. This kind of skill improvement on signal processing need specific memory device for video signal. in this paper, data latch scheme which implements CMOS flip-flop to hold Information from in-put strobe and new reading method is devised to attain a proper access time suitable for HDTY signal. Compared with conventional write scheme, data latch method has two procedures to complete write operation : bit line write and storage cell write, enabling concurrent I /0 operation at the same address. Also, fast read access is possible through the method similar to static column mode and the separated read word line.

• The KIPS Transactions:PartA
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• v.9A no.1
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• pp.93-98
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• 2002

This paper introduces the design of high-speed analog-to-digital converter (ADC) for hard disk drive (HDD) read channel applications. This circuit is bated on fast regenerative autozero comparator for high speed and low-error rate comparison operation, and Double Speed Dual ADC (DSDA) architecture for efficiently increasing the overall conversion speed of ADC. A new type of thermometer-to-binary decoder appropriate for the autozero architecture is employed for no glitch decoding, simplifying the conventional structure significantly. This ADC is designed for 6-bit resolution, 800 Msample/s maximum conversion rate, 390 mW power dissipation, one clock cycle latency in 0.65 m CMOS technology.

• Journal of IKEEE
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• v.25 no.3
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• pp.473-478
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• 2021

Although CNTFETs have attracted great attention due to their ability to increase semiconductor device performance by about 13 times, the commercialization of CNTFETs has been challenging because of the immature deposition process of CNTs. To overcome these difficulties, circuit design method considering the known limitations of the CNTFET manufacturing process is receiving increasing attention. SRAM is a major element constituting microprocessor and is regularly and repeatedly positioned in the cache memory; so, it has the advantage that CNTs can be more easily and densely deposited in SRAM than other circuit blocks. In order to take these advantages, this paper presents a circuit design method for SRAM cells considering CNT density and then evaluates its performance improvement using HSPICE simulation. As a result of simulation, it is found that when CNTFET is applied to SRAM, the gate width can be reduced by about 1.7 times and the read speed also can be improved by about 2 times when the CNT density was increased in the same gate width.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.11
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• pp.2541-2547
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• 2010

In this paper, we propose a design technique which replaces logic transistors of 1.2V with medium-voltage transistors of 3.3V having small off-leakage current in repetitive block circuits where speed is not an issue, to implement a low-power eFuse OTP memory IP in the stand-by state. In addition, we use dual-port eFuse cells reducing operational current dissipation by reducing capacitances parasitic to RWL (Read word-line) and BL (Bit-line) in the read mode. Furthermore, we propose an equivalent circuit for simulating program power injected to an eFuse from a program voltage. The layout size of the designed 512-bit eFuse OTP memory IP with a 90nm CMOS image sensor process is $342{\mu}m{\times}236{\mu}m$. It is confirmed by measurement experiments on 42 samples with a program voltage of 5V that we get a good result having 97.6 percent of program yield. Also, the minimal operational supply voltage is measured well to be 0.9V.

• Journal of IKEEE
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• v.26 no.4
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• pp.659-670
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• 2022

An 830-Mb/s/pin transceiver for a controller supporting ×32 LPDDR2 memory is designed. The transmitter consists of eight unit circuits has an impedance in the range of 34Ω ∽ 240Ω, and its impedance is controlled by an impedance correction circuit. The transmitted DQS signal has a phase shifted by 90° compared to the DQ signals. In the receive operation, the read time calibration is performed by per-pin skew calibration and clock-domain crossing within a byte. The implemented transceiver for the LPDDR2 memory controller is designed by using a 55-nm process using a 1.2V supply voltage and has a maximum signal transmission rate of 830 Mb/s/pin. The area and power consumption of each lane are 0.664 mm² and 22.3 mW, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.17-26
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• 2006

The analog Viterbi decoder for the PR (1 2 2 1) which is used for BVD read channel is designed with circular analog parallel circuits. Since the inter symbol interference is serious problem in the high density magnetic storage device or DVD, the PRML technology is normally employed for the purpose of minimizing the decoding error. The feature of the PRML technology is with the multi-level coding according to the predetermined combining rule among the neighboring symbols and with the decoding according to the known combining rule. Though the conventional PRML technology is implemented with the digital circuits, the recent trend towards this end is with the utilization of the analog circuits due to the requirements of higher speed and lower power in the DVD read channel. In this study, the Viterbi decoder which is the bottleneck of the PRML implementation is designed with the analog parallel circuit structure. The designed Viterbi decoder for the PR (1 2 2 1) signal shows 3 times faster in the speed and 1/3 times less in the power consumption than thoseoftheconventionaldigitalcounterpart.