• Journal of the Microelectronics and Packaging Society
• /
• v.8 no.3
• /
• pp.49-53
• /
• 2001

Vortical etching experiments of ($SrBi_2Ta_2O_9$)/Si thin films have been performed by using the inductively coupled plasma reactive ion etching (ICP-ME) apparatus. The purposes of these experiments are to get the effective area of vertical surface. Because this technology is very important to get good qualities of ferroelectric gate structure, capacitor and the minimum parasitic effects related to the excellent performances of the FRAM (Ferroelectric Random Access Memory) device. The reacting gases were Ar and $Cl_2$gases, and various $Ar/C1_2$flow ratios were used. The etching experiments were carried out at various RF powers such as 700, 700, 500W and at various DC powers such as 200, 150, 100, 50W, respectively. The maximum etch rate of $SrBi_2Ta_2O_9$/Si thin films was 1050 A/min at the $Ar/C1_2$ gas ratio of 20/16, RF power of 700 W and DC power of 200 W. From the SEM (scanning electron microscopy) image of the SBT thin films, the wall angle was as good as about $82^{\circ}$.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.08a
• /
• pp.393-393
• /
• 2012

Optically active nanostructures such as subwavelength moth-eye antireflective structures or surface enhanced Raman spectroscopy (SERS) active structures have been demonstrated to provide the effective suppression of unwanted reflections as in subwavelength structure (SWS) or effective enhancement of selective signals as in SERS. While various nanopatterning techniques such as photolithography, electron-beam lithography, wafer level nanoimprinting lithography, and interference lithography can be employed to fabricate these nanostructures, roll-to-roll (R2R) nanoimprinting is gaining interests due to its low cost, continuous, and scalable process. R2R nanoimprinting requires a master to produce a stamp that can be wrapped around a quartz roller for repeated nanoimprinting process. Among many possibilities, two different types of mask can be employed to fabricate optically active nanostructures. One is self-assembled Au nanoparticles on Si substrate by depositing Au film with sputtering followed by annealing process. The other is monolayer silica particles dissolved in ethanol spread on the wafer by spin-coating method. The process is optimized by considering the density of Au and silica nano particles, depth and shape of the patterns. The depth of the pattern can be controlled with dry etch process using reactive ion etching (RIE) with the mixture of SF6 and CHF3. The resultant nanostructures are characterized for their reflectance using UV-Vis-NIR spectrophotometer (Agilent technology, Cary 5000) and for surface morphology using scanning electron microscope (SEM, JEOL JSM-7100F). Once optimized, these optically active nanostructures can be used to replicate with roll-to-roll process or soft lithography for various applications including displays, solar cells, and biosensors.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.143-144
• /
• 2011

최근 광전자 분야에서는 미래 에너지 자원에 대한 관심과 함께 GaN 기반 발광다이오드에 대한 연구가 활발히 진행되고 있다. 특히 InGaN/GaN 양자 우물 구조는 푸른색, 녹색 발광다이오드 구현에 있어 우수한 물질적 특성을 가지고 있다고 알려져 있다. 하지만 우수한 물질적 특성에도 불구하고 고인듐 고품위 막질 성장의 어려움으로 인해 높은 효율의 녹색 발광다이오드 구현하는 것은 여전히 어려운 실정이다. 이를 극복하기 위한 대안 중에 하나인 선택 영역 박막성장법(Selective Area Growth)은 마스크 패터닝을 통해 열린 영역에서만 박막을 성장하는 방법으로써 인듐 함량을 향상 시킬 수 있는 방법으로 주목 받고 있다. 선택 영역 박막 성장법을 이용하여 GaN를 성장하기 위해 그림 1의 공정을 통하여 n-GaN층 위에 SiO2 마스크를 포토리소그라피와 Reactive Ion Etching (RIE)를 이용한 건식 식각 공정을 통해 형성한 후 Metal Organic Chemical Vapor Deposition (MOCVD) 장비를 이용하여 선택적으로 에피를 성장하였다. 성장된 마이크로 피라미드 발광다이오드 구조는 n-GaN 피라미드 구조위에 양자우물 및 p-GaN을 성장함으로써 p-GaN/MQW/n-GaN 구조를 갖는다. 이렇게 생성된 피라미드 구조의 에피를 이용하여 발광다이오드를 제작한 후 그에 대한 전기적, 광학적 특성을 측정하였다. 2인치 웨이퍼의 중심을 원점 좌표인 (0,0)으로 설정하였을 때 2인치 웨이퍼에서 좌표에 해당하는 위치에서의 Photoluminescence (PL) 측정한 결과 일반적인 구조의 발광다이오드의 경우 첨두치가 441~451nm인데 반해 피라미드 구조의 발광다이오드의 경우 첨두치가 558nm~563nm 임을 알 수 있었다. 이를 통해 피라미드 구조 발광다이오드의 경우 일반적인 구조의 발광다이오드에 비해 인듐의 함유량을 증가시킬 수 있다는 것을 알 수 있다. 본 논문에서는 선택 영역 박막 성장법을 이용하여 마이크로 피라미드 InGaN/GaN 양자 우물 구조 구현과 광 전기적 특성에 대해 더 자세히 논의 하도록 하겠다.

• Journal of the Microelectronics and Packaging Society
• /
• v.12 no.2 s.35
• /
• pp.129-134
• /
• 2005

Electroplating copper is the important role in formation of 3D stacking interconnection in SiP (System in Package). The I-V characteristics curves are investigated at different electrolyte conditions. Inhibitor and accelerator are used simultaneously to investigate the effects of additives. Three different sizes of via are tested. All via were prepared with RIE (reactive ion etching) method. Via's diameter are 50, 75, $100{\mu}m$ and the height is $100{\mu}m$. Inside via, Ta was deposited for diffusion barrier and Cu was deposited fer seed layer using magnetron sputtering method. DC, pulse and pulse revere current are used in this study. With DC, via cannot be filled without defects. Pulse plating can improve the filling patterns however it cannot completely filled copper without defects. Via was filled completely without defects using pulse-reverse electroplating method.

• Proceedings of the KIEE Conference
• /
• 1998.07g
• /
• pp.2518-2520
• /
• 1998

Silicon can be reactive ion etched (RIE) either isotropically or anisotropically. In this paper, a new micromachining technology combining these two etching characteristics is proposed. In the proposed method, the fabrication steps are as follows. First. a polysilicon layer, which is used as the bottom electrode, is deposited on the silicon wafer and patterned. Then the silicon substrate is etched anisotropically to a few micrometer depth that forms a cavity. Then an PECVD oxide layer is deposited to passivate the cavity side walls. The oxide layers at the top and bottom faces are removed while the passivation layers of the side walls are left. Then the substrate is etched again but in an isotropic etch condition to form a round trench with a larger radius than the anisotropic cavity. Then a sacrificial PECVD oxide layer is deposited and patterned. Then a polysilicon structural layer is deposited and patterned. This polysilicon layer forms a pivot structure of a rocker-arm. Finally, oxide sacrificial layers are etched away. This new micromachining technology is quite simpler than conventional method to fabricate joint structures, and the devices that are fabricated using this technology do not require a flexing structure for motion.

• Korean Journal of Materials Research
• /
• v.16 no.12
• /
• pp.731-738
• /
• 2006

It is seriously considered using Al CMP (chemical mechanical planarization) process for the next generation 45 nm Al wiring process. Al CMP is known that it has a possibility of reducing process time and steps comparing with conventional RIE (reactive ion etching) method. Also, it is more cost effective than Cu CMP and better electrical conductivity than W via process. In this study, we investigated 4 different kinds of slurries based on abrasives for reducing scratches which contributed to make defects in Al CMP. The abrasives used in this experiment were alumina, fumed silica, alkaline colloidal silica, and acidic colloidal silica. Al CMP process was conducted as functions of abrasive contents, $H_3PO_4$ contents and pressures to find out the optimized parameters and conditions. Al removal rates were slowed over 2 wt% of slurry contents in all types of slurries. The removal rates of alumina and fumed silica slurries were increased by phosphoric acid but acidic colloidal slurry was slightly increased at 2 vol% and soon decreased. The excessive addition of phosphoric acid affected the particle size distributions and increased scratches. Polishing pressure increased not only the removal rate but also the surface scratches. Acidic colloidal silica slurry showed the highest removal rate and the lowest roughness values among the 4 different slurry types.

• Journal of the Microelectronics and Packaging Society
• /
• v.12 no.2 s.35
• /
• pp.111-119
• /
• 2005

Stack specimen with three dimensional interconnection structure through Cu via of $75{\mu}m$ diameter, $90{\mu}m$ height and $150{\mu}m$ pitch was successfully fabricated using subsequent processes of via hole formation with Deep RIE (reactive ion etching), Cu via filling with pulse-reverse electroplating, Si thinning with CMP, photolithography, metal film sputtering, Cu/Sn bump formation, and flip chip bonding. Contact resistance of Cu/Sn bump and Cu via resistance could be determined ken the slope of the daisy chain resistance vs the number of bump joints of the flip chip specimen containing Cu via. When flip- chip bonded at $270^{\circ}C$ for 2 minutes, the contact resistance of the Cu/Sn bump joints of $100{\times}100{\mu}m$ size was 6.7m$\Omega$ and the Cu via resistance of $75{\mu}m$ diameter, $90{\mu}m$ height was 2.3m$\Omega$.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2016.02a
• /
• pp.417-417
• /
• 2016

Global environmental deterioration has become more serious year by year and thus scientific interests in the renewable energy as environmental technology and replacement of fossil fuels have grown exponentially. Photoelectrochemical (PEC) cell consisting of semiconductor photoelectrodes that can harvest light and use this energy directly to split water, also known as photoelectrolysis or solar water splitting, is a promising renewable energy technology to produce hydrogen for uses in the future hydrogen economy. A major advantage of PEC systems is that they involve relatively simple processes steps as compared to many other H2 production systems. Until now, a number of materials including TiO2, WO3, Fe2O3, and BiVO4 were exploited as the photoelectrode. However, the PEC performance of these single absorber materials is limited due to their large charge recombinations in bulk, interface and surface, leading low charge separation/transport efficiencies. Recently, coupling of two materials, e.g., BiVO4/WO3, Fe2O3/WO3 and CuWO4/WO3, to form a type II heterojunction has been demonstrated to be a viable means to improve the PEC performance by enhancing the charge separation and transport efficiencies. In this study, we have prepared a triple-layer heterojunction BiVO4/WO3/SnO2 photoelectrode that shows a comparable PEC performance with previously reported best-performing nanostructured BiVO4/WO3 heterojunction photoelectrode via a facile solution method. Interestingly, we found that the incorporation of SnO2 nanoparticles layer in between WO3 and FTO largely promotes electron transport and thus minimizes interfacial recombination. The impact of the SnO2 interfacial layer was investigated in detail by TEM, hall measurement and electrochemical impedance spectroscopy (EIS) techniques. In addition, our planar-structured triple-layer photoelectrode shows a relatively high transmittance due to its low thickness (~300 nm), which benefits to couple with a solar cell to form a tandem PEC device. The overall PEC performance, especially the photocurrent onset potential (Vonset), were further improved by a reactive-ion etching (RIE) surface etching and electrocatalyst (CoOx) deposition.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.11
• /
• pp.1-5
• /
• 2010

We developed a novel micro-electro mechanical systems (MEMS) test socket using silicon on insulator (SOI) substrate with the cantilever array structure. We designed the round shaped cantilevers with the maximum length of $350{\mu}m$, the maximum width of $200{\mu}m$ and the thickness of $10{\mu}m$ for $650{\mu}m$ pitch for 8 mm x 8 mm area and 121 balls square ball grid array (BGA) packages. The MEMS test socket was fabricated by MEMS technology using metal lift off process and deep reactive ion etching (DRIE) silicon etcher and so on. The MEMS test socket has a simple structure, low production cost, fine pitch, high pin count and rapid prototyping. We verified the performances of the MEMS test sockets such as deflection as a function of the applied force, path resistance between the cantilever and the metal pad and the contact resistance. Fabricated cantilever has 1.3 gf (gram force) at $90{\mu}m$ deflection. Total path resistance was less than $17{\Omega}$. The contact resistance was approximately from 0.7 to $0.75{\Omega}$ for all cantilevers. Therefore the test socket is suitable for BGA integrated circuit (IC) packages tests.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2003.07a
• /
• pp.319-322
• /
• 2003

To match the charge induced by the insulators $CeO_2$ with the remanent polarization of ferro electric SBT thin films, areas of Pt/SBT/Pt (MFM) and those of $Pt/CeO_2/Si$ (MIS) capacitors were ind ependently designed. The area $S_M$ of MIS capacitors to the area $S_F$ of MFM capacitors were varied from 1 to 10, 15, and 20. Top electrode Pt and SBT layers were etched with for various area ratios of $S_M\;/\;S_F$. Bottom electrode Pt and $CeO_2$ layers were respectively deposited by do and rf sputtering in-situ process. SBT thin film were prepared by the metal orgnic decomposition (MOD) technique. $Pt(100nm)/SBT(350nm)/Pt(300nm)/CeO_2(40nm)/p-Si$ (MFMIS) gate structures have been fabricated with the various $S_M\;/\;S_F$ ratios using inductively coupled plasma reactive ion etching (ICP-RIE). The leakage current density of MFMIS gate structures were improved to $6.32{\times}10^{-7}\;A/cm^2$ at the applied gate voltage of 10 V. It is shown that in the memory window increase with the area ratio $S_M\;/\;S_F$ of the MFMIS structures and a larger memory window of 3 V can be obtained for a voltage sweep of ${\pm}9\;V$ for MFMIS structures with an area ratio $S_M\;/\;S_F\;=\;6$ than that of 0.9 V of MFS at the same applied voltage. The maximum memory windows of MFMIS structures were 2.28 V, 3.35 V, and 3.7 V with the are a ratios 1, 2, and 6 at the applied gate voltage of 11 V, respectively. It is concluded that ferroelectric gate capacitors of MFMIS are good candidates for nondestructive readout-nonvolatile memories.