• 한국통신학회논문지
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• 제32권10C호
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• pp.942-949
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• 2007

In this paper, we propose a new rate-control scheme, called splining, to construct low-rate codes from high-rate codes by splitting rows of the parity-check matrices of LDPC codes, which can construct rate-compatible LDPC codes having good initial transmission performance. Good low-rate codes can be constructed by making the number of distinct check node degrees as small as possible after splitting. The proposed scheme achieves good cycle property, low decoding complexity, and fast convergence speed, especially compared to the puncturing. Especially, rate-compatible repeat accumulate-type LDPC (RA-Type LDPC) code is constructed using splitting, which covers the code rates from 1/3 to 4/5. Through simulation it is shown that this code outperforms other rate-compatible RA-Type LDPC codes for all rates and can be decoded conveniently and efficiently.

• Journal of Communications and Networks
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• 제11권5호
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• pp.455-463
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• 2009

We consider the challenges of finding good puncturing patterns for rate-compatible low-density parity-check code (LDPC) codes over additive white Gaussian noise (AWGN) channels. Puncturing is a scheme to obtain a series of higher rate codes from a lower rate mother code. It is widely used in channel coding but it causes performance is lost compared to non-punctured LDPC codes at the same rate. Previous work, considered the role of survived check nodes in puncturing patterns. Limitations, such as single survived check node assumption and simulation-based verification, were examined. This paper analyzes the performance according to the role of multiple survived check nodes and multiple dead check nodes. Based on these analyses, we propose new algorithm to find a good puncturing pattern for LDPC codes over AWGN channels.

• Journal of Communications and Networks
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• 제17권4호
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• pp.346-350
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• 2015

It is known that the progressive edge-growth (PEG) algorithm can be used to construct low-density parity-check (LDPC) codes at finite code lengths with large girths through the establishment of edges between variable and check nodes in an edge-by-edge manner. In [1], the authors derived a class of LDPC codes for relay communication systems by extending the full-diversity root-LDPC code. However, the submatrices of the parity-check matrix H corresponding to this code were constructed separately; thus, the girth of H was not optimized. To solve this problem, this paper proposes a modified PEG algorithm for use in the design of large girth and full-diversity LDPC codes. Simulation results indicated that the LDPC codes constructed using the modified PEG algorithm exhibited a more favorable frame error rate performance than did codes proposed in [1] over block-fading channels.

• 한국통신학회논문지
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• 제38A권8호
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• pp.662-668
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• 2013

무선이동통신 시스템은 무선 채널상황에 맞게 변조 파라미터와 부호율 등을 적응적으로 변화시켜 성능 이득을 얻을 수 있는 다양한 전송기법을 채택해오고 있다. 그 중에서 재전송 기법과 오류정정부호의 패리티 양을 적응적으로 조절하여 전송하는 incremental redundancy hybrid ARQ (IR-HARQ) 방식은 시스템 수율 측면에서 효율적인 것으로 알려져 있으며 다양한 무선이동통신시스템에서 사용되고 있다. 본 논문에서는 이중 대각 패리티 구조를 갖는 블록 LDPC의 IR-HARQ 방식을 제안한다. IR-HARQ 설계 시 모부호에 의해 부호화된 비트의 전송 순서가 성능을 좌우하는 것을 고려하여 전송 우선순위를 정의하고 전송 패킷 구성 규칙을 제안한다. 제안한 방식의 성능 분석을 다양한 변조 파라미터 및 부호율에서 수행하였으며, 다중 안테나 모드에 따른 시스템 수율 성능을 제시한다. 성능 분석 결과를 통해 제안한 방식은 기존의 방식에 비해 성능 이득을 얻음을 확인할 수 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권4호
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• pp.419-426
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• 2014

This paper proposes a high-throughput encoding process and encoder architecture for quasi-cyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 2011년도 하계학술대회
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• pp.133-134
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• 2011

본 논문에서는 소스코딩에 활용되고 있는 LDPCA 부호를 가변 부호율을 얻는 채널코딩 목적으로써의 사용 가능성을 타진한다. 컴퓨터 성능 실험의 결과로 가변 부호율과 어느 정도의 BER 성능을 확인하였지만, 체크노드 머징기법이 여타의 LDPC 부호에 비해 성능을 크게 떨어뜨리는 것으로 나타났다. 향후 체크노드 머징이 가능하면서도 좀 더 개선된 성능을 가지는 LDPCA 를 설계하는 일이 중요할 것으로 생각된다.