• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10C
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• pp.942-949
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• 2007

In this paper, we propose a new rate-control scheme, called splining, to construct low-rate codes from high-rate codes by splitting rows of the parity-check matrices of LDPC codes, which can construct rate-compatible LDPC codes having good initial transmission performance. Good low-rate codes can be constructed by making the number of distinct check node degrees as small as possible after splitting. The proposed scheme achieves good cycle property, low decoding complexity, and fast convergence speed, especially compared to the puncturing. Especially, rate-compatible repeat accumulate-type LDPC (RA-Type LDPC) code is constructed using splitting, which covers the code rates from 1/3 to 4/5. Through simulation it is shown that this code outperforms other rate-compatible RA-Type LDPC codes for all rates and can be decoded conveniently and efficiently.

• Journal of Communications and Networks
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• v.11 no.5
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• pp.455-463
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• 2009

We consider the challenges of finding good puncturing patterns for rate-compatible low-density parity-check code (LDPC) codes over additive white Gaussian noise (AWGN) channels. Puncturing is a scheme to obtain a series of higher rate codes from a lower rate mother code. It is widely used in channel coding but it causes performance is lost compared to non-punctured LDPC codes at the same rate. Previous work, considered the role of survived check nodes in puncturing patterns. Limitations, such as single survived check node assumption and simulation-based verification, were examined. This paper analyzes the performance according to the role of multiple survived check nodes and multiple dead check nodes. Based on these analyses, we propose new algorithm to find a good puncturing pattern for LDPC codes over AWGN channels.

• Journal of Communications and Networks
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• v.17 no.4
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• pp.346-350
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• 2015

It is known that the progressive edge-growth (PEG) algorithm can be used to construct low-density parity-check (LDPC) codes at finite code lengths with large girths through the establishment of edges between variable and check nodes in an edge-by-edge manner. In [1], the authors derived a class of LDPC codes for relay communication systems by extending the full-diversity root-LDPC code. However, the submatrices of the parity-check matrix H corresponding to this code were constructed separately; thus, the girth of H was not optimized. To solve this problem, this paper proposes a modified PEG algorithm for use in the design of large girth and full-diversity LDPC codes. Simulation results indicated that the LDPC codes constructed using the modified PEG algorithm exhibited a more favorable frame error rate performance than did codes proposed in [1] over block-fading channels.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.8
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• pp.662-668
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• 2013

Mobile communication systems have been adopting link adaptive transmission schemes such as adaptive modulation and coding (AMC) and hybrid-ARQ (HARQ). Incremental redundancy (IR) HARQ scheme is known to be highly efficient in terms of throughput and power consumption and can be a good solution for mobile communication systems. In this paper, we propose an IR-HARQ scheme based on dual-diagonal parity-type block LDPC codes in which we define a transmission priority of coded bits and propose the sub-packet construction rule. We present the throughput performance of IR-HARQ with various modulation and coding and multi-antenna modes. Consequently, the proposed scheme provides the improvement of system throughput by elaborate link adaptation with CQI information.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.419-426
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• 2014

This paper proposes a high-throughput encoding process and encoder architecture for quasi-cyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2011.07a
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• pp.133-134
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• 2011

본 논문에서는 소스코딩에 활용되고 있는 LDPCA 부호를 가변 부호율을 얻는 채널코딩 목적으로써의 사용 가능성을 타진한다. 컴퓨터 성능 실험의 결과로 가변 부호율과 어느 정도의 BER 성능을 확인하였지만, 체크노드 머징기법이 여타의 LDPC 부호에 비해 성능을 크게 떨어뜨리는 것으로 나타났다. 향후 체크노드 머징이 가능하면서도 좀 더 개선된 성능을 가지는 LDPCA 를 설계하는 일이 중요할 것으로 생각된다.