• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.11
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• pp.5610-5624
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• 2017

A novel scheme based on polarization modulation and the weighted fractional Fourier transform (PM-WFRFT) is proposed in this paper to enhance the physical layer security of dual-polarized satellite systems. This scheme utilizes the amplitude and phase of the carrier as information-bearing parameters to transmit the normal signal and conceals the confidential information in the carrier's polarization state (PS). After being processed by WFRFT, the characteristics of the transmit signal (including amplitude, phase and polarization state) vary randomly and in nearly Gaussian distribution. This makes the signal very difficult for an eavesdropper to recognize or capture. The WFRFT parameter is also encrypted by a pseudo-random sequence and updated in real time, which enhances its anti-interception performance. Furthermore, to prevent the polarization-based impairment to PM-WFRFT caused by depolarization in the wireless channel, two components of the polarized signal are transmitted respectively in two symbol periods; this prevents any mutual interference between the two orthogonally polarized components. Demodulation performance in the system was also assessed, then the proposed scheme was validated with a simulated dual-polarized satellite system.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.443-450
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• 2014

This paper presents a 20-Gb/s optical receiver circuit fabricated with standard 65-nm CMOS technology. Our receiver circuits are designed with consideration for parasitic inductance and capacitance due to bonding wires connecting the photodetector and the circuit realized separately. Such parasitic inductance and capacitance usually disturb the high-speed performance but, with careful circuit design, we achieve optimized wide and flat response. The receiver circuit is composed of a transimpedance amplifier (TIA) with a DC-balancing buffer, a post amplifier (PA), and an output buffer. The TIA is designed in the shunt-feedback configuration with inductive peaking. The PA is composed of a 6-stage differential amplifier having interleaved active feedback. The receiver circuit is mounted on a FR4 PCB and wire-bonded to an equivalent circuit that emulates a photodetector. The measured transimpedance gain and 3-dB bandwidth of our optical receiver circuit is 84 $dB{\Omega}$ and 12 GHz, respectively. 20-Gb/s $2^{31}-1$ electrical pseudo-random bit sequence data are successfully received with the bit-error rate less than $10^{-12}$. The receiver circuit has chip area of $0.5mm{\times}0.44mm$ and it consumes excluding the output buffer 84 mW with 1.2-V supply voltage.

• The KIPS Transactions:PartC
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• v.13C no.3 s.106
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• pp.311-316
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• 2006

We propose the optical sensor network using optical CDMA with bipolar receiver and modified Pseudorandom Noise codes which are widely used in the wireless communication network. We numerically analyze the performances in the optical sensor network. In the proposed network, multiple access interferences between two sensors are suppressed by performing synchronization between the optical encoder and the optical decoder and adjusting the delay times of optical delay lines. Numerical simulations confirm that the performance can be acquired by suppressing the beat noise among optical signals as the number of sensors increases.

• The KIPS Transactions:PartB
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• v.10B no.5
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• pp.479-484
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• 2003

We propose a blind watermarking method that embeds a binary pseudo-random sequence (watermarks), (-1, 1), into wavelet dc components, while most watermarking techniques embed watermarks in the middle frequency range for robustness and fidelity. In our scheme, the watermarks are embedded into particular locations to be selected by a key, where some watermark embeddings are skipped to avoid severe degradation in quality. Our robustness is compared to some results registered to the ChechMark [1] that is one of the most popular benchmarking tools.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.10B
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• pp.1216-1221
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• 2011

We propose a multiplexed fiber Bragg grating (FBG) sensor network for vessel monitoring to measure the variation of strain and temperature by environmental perturbation based on code division multiple access (CDMA). The center wavelength of FBG was linearly changed by environmental perturbation such as strain and temperature variation so that we could be monitoring the state of sensors. A RSOA was used as optical broadband source and which was modulated by using pseudo random binary sequence (PRBS) signal. The correlation peak of reflected signal from sensor networks was measured. In this paper, we used the sliding correlation techniques for high speed response and dynamic rage of sensors.

• ETRI Journal
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• v.33 no.5
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• pp.752-758
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• 2011

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter-rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead-zone problem of charge pump circuit. A voltage-controlled oscillator is designed with a 'Mode' switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak-to-peak jitter is 24.89 ps under $2^{31}-1$ bit-long pseudo-random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm${\times}$1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 ${\mu}m$ CMOS process.

• 제어로봇시스템학회:학술대회논문집
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• 1998.10a
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• pp.451-454
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• 1998

This paper proposes a new method of Model Predictive Control (MPC) of nonlinear process by us-ing the measured Volterra kernels as the nonlinear model. A nonlinear dynamical process is usually de-scribed as Volterra kernel representation, In the authors' method, a pseudo-random M-sequence is ar plied to the nonlinear process, and its output is measured. Taking the crosscorrelation between the input and output, we obtain the Volterra kernels up to 3rd order which represent the nonlinear characteristics of the process. By using the measured Volterra kernels, we can construct the nonlinear model for MPC. In applying Model Predictive Control to a nonlinear process, the most important thing is, in general, what kind of nonlinear model should be used. The authors used the measured Volterra kernels of up to 3rd order as the process model. The authors have carried out computer simulations and compared the simulation results for the linear model, the nonlinear model up to 2nd Volterra kernel, and the nonlinear model up to 3rd order Vol-terra kernel. The results of computer simulation show that the use of Valterra kernels of up to 3rd order is most effective for Model Predictive Control of nonlinear dynamical processes.

• Journal of Korea Multimedia Society
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• v.14 no.5
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• pp.595-606
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• 2011

This paper proposes a robust watermarking scheme for GIS digital map by using the geometric properties of polyline and polygon, which are the fundamental components in vector data structure. In the proposed scheme, we calculate the lengths and the perimeters of all polylines and polygons in a map and cluster them to a number of groups. Then we embed the binary watermark by changing the mean of lengths and perimeters in an embedding group. For improving the safety and robustness, we permute the binary watermark through PRNS(pseudo-random number sequence) processing and embed it repeatedly in a model. Experimental results verified that our scheme has a good invisibility, safety and robustness to various geometric attacks and also our scheme needs not the original map in the extracting process of watermark.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.73-76
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• 2010

A two-facet approach was used to investigate the parametric performance of functional high-speed DDR3 (Double Data Rate) DRAM (Dynamic Random Access Memory) die placed in different types of BGA (Ball Grid Array) packages: wire-bonded BGA (FBGA, Fine Ball Grid Array), flip-chip (FCBGA) and lead-bonded $microBGA^{(R)}$. In the first section, packaged live DDR3 die were tested using automatic test equipment using high-resolution shmoo plots. It was found that the best timing and voltage margin was obtained using the lead-bonded microBGA, followed by the wire-bonded FBGA with the FCBGA exhibiting the worst performance of the three types tested. In particular the flip-chip packaged devices exhibited reduced operating voltage margin. In the second part of this work a test system was designed and constructed to mimic the electrical environment of the data bus in a PC's CPU-Memory subsystem that used a single DIMM (Dual In Line Memory Module) socket in point-to-point and point-to-two-point configurations. The emulation system was used to examine signal integrity for system-level operation at speeds in excess of 6 Gb/pin/sec in order to assess the frequency extensibility of the signal-carrying path of the microBGA considered for future high-speed DRAM packaging. The analyzed signal path was driven from either end of the data bus by a GaAs laser driver capable of operation beyond 10 GHz. Eye diagrams were measured using a high speed sampling oscilloscope with a pulse generator providing a pseudo-random bit sequence stimulus for the laser drivers. The memory controller was emulated using a circuit implemented on a BGA interposer employing the laser driver while the active DRAM was modeled using the same type of laser driver mounted to the DIMM module. A custom silicon loading die was designed and fabricated and placed into the microBGA packages that were attached to an instrumented DIMM module. It was found that 6.6 Gb/sec/pin operation appears feasible in both point to point and point to two point configurations when the input capacitance is limited to 2pF.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.11
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• pp.581-588
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• 2007

In Digital Right Management, symmetric cipher is used for content encryption to reduce encryption cost, AES, advanced encryption standard is usually used to multimedia encryption under desktop environment because of its reasonable security level and computation cost. But mobile handheld device often uses slow speed processor and operates under battery-powered environment. Therefore it requires low computation cost and low energy consumption. This paper proposes new stream cipher scheme which combines pseudo random number generator(PRNG) and dynamically generated permutations. Proposed scheme activates PRNG and generates original key streams. Then it generates extended key streams by applying permutation to original sequence. These extended key streams are XORed with plaintext and generate ciphertext. Proposed scheme reduces the usage of PRNG. Therefore this scheme is fast and consumes less energy in comparison with normal stream cipher. Especially, this scheme shows great speed up (almost 2 times) than normal stream cipher scheme in random access.