• Journal of Institute of Control, Robotics and Systems
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• v.22 no.8
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• pp.671-677
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• 2016

A Controller Area Network (CAN) is a serial communication protocol that is highly reliable and efficient in many aspects, such as wiring cost and space, system flexibility, and network maintenance. Therefore, it is chosen for the communication protocol between a single chip controller based on Field Programmable Gate Array (FPGA) and peripheral devices. In this paper, the design and implementation of CAN IP, which is written in VHSIC Hardware Description Language (VHDL), is presented. The implemented CAN IP is based on the CAN 2.0A specification. The CAN IP consists of three processes: clock generator, bit timing, and bit streaming. The clock generator process generates a time quantum clock. The bit timing process does synchronization, receives bits from the Rx port, and transmits bits to the Tx port. The bit streaming process generates a bit stream, which is made from a message received from a micro controller subsystem, receives a bit stream from the bit timing process, and handles errors depending on the state of the CAN node and CAN message fields. The implemented CAN IP is synthesized and downloaded into SmartFusion FPGA. Simulations using ModelSim and chip test results show that the implemented CAN IP conforms to the CAN 2.0A specification.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2120-2130
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• 1998

This paper concerns a design of programmable MPEG decoder for video processing by object unit on network. The decoder can process video data effectively by a embedded controller with stack buffers for supporting OOP (Object-Oriented Programming). The controller offers extended instructions that process several data types including 32bit integer type. In addition to that, we have a vector processor, in this decoder that can execute advanced compensation and prediction by half pixel and SA(Shape Adaptive)-IDCT of MPEG-4. Absolutors and halfers in the vector processor make this architecture extensive to a encoder. We verified the decoder with $0.6\mu\textrm{m}$ 5-Volt CMOS COMPASS library.

• Korean Journal of Fisheries and Aquatic Sciences
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• v.54 no.5
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• pp.798-807
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• 2021

The directivity characteristics of acoustic transducers for conventional single-beam echo sounders considerably limit the detection of fish-size information in acoustic field surveys. To overcome this limitation, using the split-aperture technique to estimate the direction of arrival of single-echo signals from individual fish distributed within the sound beam represents the most reliable method for fish-size classification. For this purpose, we design and develop a split-beam data acquisition and processing system to obtain fish-size information in conjunction with a 50-kHz single-beam echo sounder. This split-beam data acquisition and processing system consists of a notebook PC, a field-programmable gate array board, an external single-transmitter module with a matching network, and four-channel receiver modules operating at a frequency of 50-kHz. The functionality of the developed split-beam data processor is tested and evaluated. Acoustic measurements in an experimental water tank showed that the developed data acquisition and processing system can be used as a fish-sizing echo sounder to estimate the size distribution of individual fish, although an external single-transmitter module with a matching network is required.

• International Journal of Computer Science & Network Security
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• v.22 no.9
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• pp.414-426
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• 2022

Elliptic Curve Cryptography (ECC) is one of the finest cryptographic technique of recent time due to its lower key length and satisfactory performance with different hardware structures. In this paper, a High Throughput Multiplier architecture is introduced for Elliptic Cryptographic applications based on concurrent computations. With the aid of the concurrent computing approach, the High Throughput Concurrent Computation (HTCC) technology that was just presented improves the processing speed as well as the overall efficiency of the point-multiplier architecture. Here, first and second distinct group operation of point multiplier are combined together and synthesised concurrently. The synthesis of proposed HTCC technique is performed in Xilinx Virtex - 5 and Xilinx Virtex - 7 of Field-programmable gate array (FPGA) family. In terms of slices, flip flops, time delay, maximum frequency, and efficiency, the advantages of the proposed HTCC point multiplier architecture are outlined, and a comparison of these advantages with those of existing state-of-the-art point multiplier approaches is provided over GF(2¹⁶³), GF(2²³³) and GF(2²⁸³). The efficiency using proposed HTCC technique is enhanced by 30.22% and 75.31% for Xilinx Virtex-5 and by 25.13% and 47.75% for Xilinx Virtex-7 in comparison according to the LC design as well as the LL design, in their respective fashions. The experimental results for Virtex - 5 and Virtex - 7 over GF(2²³³) and GF(2²⁸³)are also very satisfactory.

• Journal of Communications and Networks
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• v.1 no.3
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• pp.201-212
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• 1999

This paper studies the rapid design and implementation of the medium access control(MAC) and related interface circuits for 802.11 wireless LANs based on the field programmed gate ar-ray(FPGA) technology. Our design is thus aimed to support both the distributed coordination function (DCF) and the point coordination function(PCF) with the aid of FPGA technology. Further-more, in an infrastructure network, some stations may serve as the access points (APs) which may function like a learning bridge. This paper will also discuss how to design for such application. The hardware of the MAC and interface may at least consist of three major parts: wireless transmission and reception processes and in-terface, host(bus) interface, and the interface to the distributed system (optional). Through the increasing popularity of FPGA de-sign, this paper presents how Complex Programmable Logic De-vices(CPLD) can be utilized for speedy design of prototypes. It also demonstrates that there is much room for low-cost hardware prototype design to accelerate the processing speed of the MAC control function and for field testing.

• The Bulletin of The Korean Astronomical Society
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• v.40 no.2
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• pp.44.1-44.1
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• 2015

We set up a project to make spectrometers for single dish observations of the Korean VLBI Network (KVN), a new future multi-beam receiver of the ASTE (Atacama Submillimeter Telescope Experiment), and the total power (TP) antennas of the Atacama Large Millimeter/submillimeter Array (ALMA). Traditionally, spectrometers based on ASIC (Application-Specific Integrated circuit) and FPGA (Field-Programmable Gate Array) have been used in radio astronomy. It is, however, that a Graphics Processing Unit (GPU) technology is now viable for spectrometers due to the rapid improvement of its performance. A high-resolution spectrometer should have the following functions: poly-phase filter, data-bit conversion, fast Fourier transform, and complex multiplication. We wrote a program based on CUDA (Compute Unified Device Architecture) for a GPU spectrometer. We measured its performance using two GPU cards, Titan X and K40m, from NVIDIA. A non-optimized GPU code can process a data stream of around 2 GHz bandwidth, which is enough for the KVN spectrometer and promising for the ASTE and ALMA TP spectrometers.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.26 no.11
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• pp.97-103
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• 2012

The basic processing unit for instant ramen noodles includes mixing, rolling, boiling, frying, cooling, and packing processes. For uniform thickness of dough sheets in rolling process, the roll-gap in rolling process needs to keep uniform thickness of flour sheets in spite of different kinds of raw materials. In this paper, we have developed a roll gap adjustment system using a PLC (Programmable Logic Controller) with a touch panel and an AC servo-mechanism to make dough sheets with a good gluten starch-network structure and uniform thickness and to contribute to process standardization by transferring from tacit knowledge of skilled workers to explicit knowledge. The developed system can adjust the roll gap in units of 0.01mm and correspond to various product items which have different thickness specification by recalling the presetting values of the desired thickness from database.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.5 no.2
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• pp.96-100
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• 2012

Existing, widely used industrial controller programmable logic controller (PLC) using the high cost and maintenance was a difficult problem. In addition, the network configuration was not easy. Thus, the filter press by remote control and management to improve productivity and shorten maintenance time. Variety of smart devices (smart phones, iPad, tablet PC, etc.) Remote control is possible by utilizing the existing controlled by the PLC addresses maintenance and improved performance compared to that of possible filter press control and management system was developed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.11
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• pp.2365-2374
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• 1997

This paper describes two algorithms for technology mapping of multiple output functions into interesting and pupular FPGAs(Field Programmable Gate Array) that use look-yp table memories. For improvement of technology mapping for FPGA, we use the functional decompoition method for multiple output functions. Two algorithms are proposed. The one is the Roth-Karpalgorithm extended for multiple output functions. The other is the efficient algorithm which looks for common decomposition functions through the decomposition procedure. The cost function is used to minimize the number of CLBs and nets and to improve performance of the network. Finally we compare our new algorithm with previous logic design technique. Experimental resutls show sigificant reduction in the number of CLBs and nets.

• International Journal of Advanced Culture Technology
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• v.4 no.4
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• pp.30-37
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• 2016

In this paper, the method of controlling the clock that is inputted on the hardware from the application, and the hardware design method are to be proposed. When the hardware is synthesized to the Field Programmable Gate Array(FPGA), the input clock is fixed, and when the input clock is changed, the synthesis process must be passed again to require more time. To solve this problem, the Mixed-Mode Clock Manager(MMCM) module is mounted to control the MMCM module from the application. The controlled MMCM module controls the input clock of the module. The experiment was process the Neural Network algorithm in the x86 CPU and SIMT based processor mounted the FPGA. The results of the experiment, SIMT-based processors, the time that is processed at a frequency of 50MHz was 77ms, 100MHz was 34ms. There was no additional synthesis time due to a change of the clock frequency.