• Journal of the Korean Society of Systems Engineering
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• v.13 no.2
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• pp.9-17
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• 2017

Concept development of a real-time Field Programmable Gate Array (FPGA)-based switched Ethernet data communication network for the Man-Machine Interface System (MMIS) is presented in this paper. The proposed design discussed in this research is based on the systems engineering (SE) approach. The design methodology is effectively developed by defining the concept development stage of the life-cycle model consisting of three successive phases, which are developed and discussed: needs analysis; concept exploration; and concept definition. This life-cycle model is used to develop an FPGA-based time-triggered Ethernet (TTE) switched data communication network for the non-safety division of MMIS system to provide real-time data transfer from the safety control systems to the non-safety division of MMIS and between the non-safety systems including control, monitoring, and information display systems. The original IEEE standard 802.3 Ethernet networks were not typically designed or implemented for providing real-time data transmission, however implementing a network that provides both real-time and on-demand data transmission is achievable using the real-time Ethernet technology. To develop the design effectively, context diagrams are implied. Conformance to the stakeholders needs, system requirements, and relevant codes and standards together with utilizing the TTE technology are used to analyze, synthesize, and develop the MMIS non-safety data communication network of the APR1400 nuclear power plant.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.6
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• pp.1346-1355
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• 2005

Recently, the development of passive optical networks (PON) for FTTH (Fiber-To-The-Home) have been actively conducted. In PON, a burst-mode transceiver is one of key modules. In this paper, we have made the protype module of a 155.52 Mpbs optical burst-mode transceiver with commercially available chips and then have measured the performance. Also, a new method of burst-mode clock recovery have been proposed. The burst-mode clock recovery implemented by using CPLD(Complex Programmable Logic Device) has coupled with the above burst-mode transceiver and has been tasted.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.12
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• pp.5654-5668
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• 2018

Driven by security and real-time demands of Internet of Things (IoT), the timing of fog computing and edge computing have gradually come into place. Gateways bear more nearby computing, storage, analysis and as an intelligent broker of the whole computing lifecycle in between local devices and the remote cloud. In fog computing, the edge broker requires X-aware capabilities that combines software programmability, stream processing, hardware optimization and various connectivity to deal with such as security, data abstraction, network latency, service classification and workload allocation strategy. The prosperous of Field Programmable Gate Array (FPGA) pushes the possibility of gateway capabilities further landed. In this paper, we propose a software-defined gateway (SDG) scheme for fog computing paradigm termed as Fog Computing Zero-Knowledge Gateway that strengthens data protection and resilience merits designed for industrial internet of things or highly privacy concerned hybrid cloud scenarios. It is a proxy for fog nodes and able to integrate with existing commodity gateways. The contribution is that it converts Privacy-Enhancing Technologies rules into provable statements without knowing original sensitive data and guarantees privacy rules applied to the sensitive data before being propagated while preventing potential leakage threats. Some logical functions can be offloaded to any programmable micro-controller embedded to achieve higher computing efficiency.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.9 no.2
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• pp.462-469
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• 2008

In this paper, we design the FPGA (Field-Programmable Gate Array) of the KOINONIA WPAN (Wireless Personal Area Network), and implement the SoC (System on Chip). We use the redundant bits to make a constant-amplitude in a modulator part. Additionally, the SNR (Signal to Noise Ratio) performance of the demodulator is improved by using the redundant bits in decoding steps. The four-million FPGA of the KOINONIA WPAN can be operated at 44MHz frequency. The PER (Packet Error Rate) of the designed FPGA with RF (Radio Frequency) module is below 1% at the -86dB MIPLS (Minimum Input Power Level Sensitivity), and the SNR is about 13dB. The SoC is implemented by using Hynix 0.25um CMOS (Complementary Metal Oxide Semiconductor) process. The size of the SoC is $6.52mm{\times}6.92mm$.

• Journal of the Korean Institute of Intelligent Systems
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• v.19 no.1
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• pp.145-151
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• 2009

Orthogonal Frequency Division Multiplexing (OFDM) has been focused on as 4th generation communication method for realization of Ubiquitous Network in land mobile communications services, and has been a standard technology of Wireless Local Area Network (WLAN) for a High Date Rate communication. And in maritime data communication using high frequency (HF) band, 32-point FFT OFDM system is recommended by International Telecommunication Union (ITU). Maritime communication should be kept on connecting when maritime accident or the maritime disaster happen. Therefore, main device FFT should be operated with low power consumption. In this paper we propose a low power 32-point FFT algorithm using radix-2 and radix-4 for low power operation. The proposed algorithm was designed using VHSIC hardware description language (VHDL), and it was confirmed that the output value of Spartan-3 field-programmable gate array (FPGA) board corresponded to the output value calculated using Matlab. The proposed 32-point FFT algorithm will be useful as a leading technology in a HF maritime data communication.

• Journal of Platform Technology
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• v.8 no.2
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• pp.22-31
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• 2020

The construction and operation of industrial automation has been actively taking place from manufacturing plan to production for improving operational efficiency of production line and flexibility of equipment. ISO/TC184 is standardizing on operating methods that can share information of programmable device controllers such as PLC and IoT that are geographically distributed in the production line. In this study, the design of the cell controller consists of PLC group and IoT group that perform signals such as temperature sensors, gas sensors, and pressure sensors for thermal processes and corresponding motors or valves. The operation and analysis of the cell controller were performed using SDN(Software Defined Network) and the three types of process services performed in thermal processes are real-time transmission service, loss-sensitive large-capacity transmission service, and normal transmission service. The simulation result showed that the average loss rate improved by about 17% when the traffic increased before and after the application of the SDN route technique, and the delay in the real-time service was as low as 1 ms.

• The Journal of Society for e-Business Studies
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• v.20 no.4
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• pp.1-17
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• 2015

A river water level monitoring system which prevents salt water damages and effectively excludes floods has been developed to contribute efficient operation of Nakdong river estuary barrage. The system can be used for monitoring upstream conditions more quickly and do appropriate responses over changes. Telemetry and telecontrols using PLCs have been built at the three sites that directly influence on the operation of barrage gates, and are linked to Nakdong river estuary barrage's IOS (Integrated Operation System) through public communication networks. By using PLC, the system can achieve even higher reliability and versatility than before as well as easy management. By power control devices, we can remotely control the power of PLCs to treat the minor troubles instantly without going on-sites. The power control devices also save data in preparation for the cases of communication failures. The system uses ADSL (FTTH) as a main network between SCADA server and PLCs, and CDMA (M2M) as a secondary network. In order to compensate security vulnerabilities of public communication network, we have installed the VPNs for secure communication between center and the observation stations, just like a dedicated network. Generally, river water level observations have been used custom-manufactured remote terminals to suit their special goals. However, in this case, we have established a system with open architecture considering the interface between different systems, the ease of use and maintenance, security, price, etc.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.31-38
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• 2008

This paper describes sensor network system implementation for the IEEE 1451.2 standard which guarantees compatibilities between various wired sensors. The proposed system consists of the Network Capable Application Processor(NCAP) in the IEEE 1451.0, the Transducer Independent Interface(TII) in the IEEE 1451.2, the Transducer Electronic Data Sheet(TEDS) and sensors. The research goal of this study is to minimize and optimize system complexity for IC design. The NCAP is implemented using C language in personal computer environment. TII is used in the parallel port between PC and an FPGA application board. Transducer is implemented using Verilog on the FPGA application board. We verified the proposed system architecture based on the standards.

• ETRI Journal
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• v.42 no.4
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• pp.505-517
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• 2020

The increasing size and complexity of deep neural networks (DNNs) necessitate the development of efficient high-performance accelerators. An efficient memory structure and operating scheme provide an intuitive solution for high-performance accelerators along with dataflow control. Furthermore, the processing of various neural networks (NNs) requires a flexible memory architecture, programmable control scheme, and automated optimizations. We first propose an efficient architecture with flexibility while operating at a high frequency despite the large memory and PE-array sizes. We then improve the efficiency and usability of our architecture by automating the optimization algorithm. The experimental results show that the architecture increases the data reuse; a diagonal write path improves the performance by 1.44× on average across a wide range of NNs. The automated optimizations significantly enhance the performance from 3.8× to 14.79× and further provide usability. Therefore, automating the optimization as well as designing an efficient architecture is critical to realizing high-performance DNN accelerators.

• Proceedings of the Korea Water Resources Association Conference
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• 1989.07a
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• pp.89-94
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• 1989

본 연구는 하천 수질의 종합관리를 위한 sotware 시스템과 hardware 시스템을 개발하는 것이다. Software 시스템은 하천의 오염실태 조사분석 자료를 활용하여 예측모형의 반응식과 제 계수를 도출하고, 수질변동 및 예측모형의 중요지표 수질인자들에 대한 시각적 화면 display 를 위한 그래픽 모듈과 우리나라 오염심화 하천에 알맞는 종합수질 관리용 컴퓨터 프로그램을 개발하므로서 궁극적으로 하천의 한정된 수자원의 최적 활용을 위한 정량적, 정성적 종합수질 관리 시스템을 개발하는 것이다. 또한, Hardware 시스템은 지표 수질인자들을 자동 측정하여 on line, real time 으로 운영 될수 있는 computer supported monitoring network system 과 수질관리를 위한 지역적 수질정보를 위한 network system 을 연구하므로서 control computer system 및 programmable process controllers system 을 구축하고자 한다.