• Nuclear Engineering and Technology
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• v.50 no.5
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• pp.780-787
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• 2018

This article presents a security module based on a field programmable gate array (FPGA) to mitigate man-in-the-middle cyber attacks. Nowadays, the FPGA is considered to be the state of the art in nuclear power plants I&C systems due to its flexibility, reconfigurability, and maintainability of the FPGA technology; it also provides acceptable solutions for embedded computing applications that require cybersecurity. The proposed FPGA-based security module is developed to mitigate information-gathering attacks, which can be made by gaining physical access to the network, e.g., a man-in-the-middle attack, using a cryptographic process to ensure data confidentiality and integrity and prevent injecting malware or malicious data into the critical digital assets of a nuclear power plant data communication system. A model-based system engineering approach is applied. System requirements analysis and enhanced function flow block diagrams are created and simulated using CORE9 to compare the performance of the current and developed systems. Hardware description language code for encryption and serial communication is developed using Vivado Design Suite 2017.2 as a programming tool to run the system synthesis and implementation for performance simulation and design verification. Simple windows are developed using Java for physical testing and communication between a personal computer and the FPGA.

• The Journal of Korean Institute of Next Generation Computing
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• v.15 no.2
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• pp.7-16
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• 2019

Neural networks can be implemented in variety of ways, and specialized chips is being developed for hardware improvement. In order to apply such neural networks to wearable devices, the compactness and the low power operation are essential. In this point of view, a suitable implementation method is a digital circuit design using field programmable gate array (FPGA). To implement this system, the learning algorithm which takes up a large part in neural networks must be implemented within FPGA for better performance. In this paper, a back propagation algorithm among various learning algorithms is implemented using FPGA, and this neural network is verified by OR gate operation. In addition, it is confirmed that this neural network can be used to analyze various users' bio signal measurement results by learning algorithm.

• 제어로봇시스템학회:학술대회논문집
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• 1992.10a
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• pp.31-36
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• 1992

This paper describes the development of a 'General-purpose ETRI MAP interface module' (GEM) for a Mini-MAP network. GEM operates as a Mini-MAP node in our FA system. To communicate between GEM and programmable devices such as PLC, CNC, and robot, RS232C is used, which is a traditional method. A Mini-MAP host system controls and monitors programmable devices via GEM. The Mini-MAP function of GEM is implemented and tested on the basis of the MAP V3.0.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.145-148
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• 1999

The ability to rapidly create and deploy new and novel services in response to market demands will be the key factor in determining the success of the future service provider. This goal may be approached from different directions. One of them is an open interface making the functionalities of a network element programmable and usable by outside entities. In this paper, we describe several aspects of this new, hot technical area and introduce related standard activities. In addition, we present a new switching system called MSMP (Multi-Service Multi-Plug-In), which is based on the open programmable interface concept, and describe its architecture and main functionalities of its components.

• Journal of the Institute of Convergence Signal Processing
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• v.15 no.4
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• pp.169-175
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• 2014

NG-SDH system is connected with networks throughout optical fibers. Network synchronization controller is a necessary for the data synchronization in each optical transmission system. In this paper, we have design and implementation the network synchronization controller using SOPC(system on a programmable chip) design technic. For this network synchronization controller we use FPGA in Altera. FPGA includes 32bit CPU, DPRAM(dual port ram), digital input/output port, transmitter and receiver framer, phase difference detector. We also confirm that designed network synchronization controller satisfies the ITU-T G.813 timing requirements.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.313-316
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• 1998

Inspired by the principle of the open market, a future network service model is forced to permit a much greater degree of flexibility, reconfigurability, programmability, protability and maintainability in telecommunication infrastructure. In this paper, one of standardization activities for the open programmable network model, IEEE standardization project P1520 (Application Programming Interfaces for Networks), is discussed.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.89.4-89
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• 2002

$\textbullet$ Field Programmable Gate Array $\textbullet$ flexible hardware $\textbullet$ neural network $\textbullet$ determinism learning $\textbullet$ multi-valued logic $\textbullet$ disjunctive normal form $\textbullet$ multi-dimensional exclusive OR

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.53-56
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• 2003

Ethernet is one of the most successful LAN technologies. Now gigabit ethernet is available in real network and some network interface cards(NIC) supports TCP segment offloading (TSO), IP checksum offloading(ICO), Jumbo frame and interrupt moderation. If we use this features appropriately, we obtain high throughput with low CPU utilization. This paper represents the network performance by varying above features.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.37 no.9
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• pp.663-670
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• 1988

Advances in VLSI technology have made it possible to have a larger number of processing elements to be included in highly parallel processor system. A system with a large number of processing elements and memory requires a complex data path. Multistage Interconnection networks(MINS) are useful in providing programmable data path between processing elements and memory modules in multiprocessor system. In this thesis, the performance of MINS for the star network has been analyzed and compared with other networks, such as generalized shuffle network, delta network, and referenced crossbar network.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.752-755
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• 1997

In this paper, a scheduling algorithm is proposed for a programmable logic controller(PLC) with remote I/Os, assuming the multi-tasking facilities. Since sequence programs are executed on the application processor and I/O data are transmitted by the network processor concurrently, the proposed algorithm schedules the data transmission as well as the sequence program execution. The suggested algorithm guarantees the bounded WCRT(worst case response time), which is the one third of the WCRT in the absence of scheduling. Computer simulation shows that the algorithm can be easily applied to a real PLC without critical constraints on utilization of resources and inter-relation among tasks.