• Journal of the Microelectronics and Packaging Society
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• v.8 no.4
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• pp.59-65
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• 2001

Epoxy/$BaTiO_3$composite capacitor films with excellent stability at room temperature, uniform thickness, and electrical properties over a large area ware successfully fabricated. The composite capacitor films with good film formation capability and easy process ability were made from epoxy resin developed for ACF as a matrix and two kinds of $BaTiO_3$powders as fillers to increase the dielectric constant of the composite film. The crystal structure of the powders and its effects on dielectric constant of the films were investigated by X-ray diffraction (XRD). And the optimum amount of dispersant, phosphate ester, was determined by viscosity measurement of suspension. DSC and dielectric property tests were conducted to decide the right curing temperature and the optimum amount of the curing agent. As a result, the capacitors of 7 $\mu \textrm{m}$ thick film with 10 nF/$\textrm{cm}^2$ and low leakage current were successfully demonstrated.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.3
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• pp.29-36
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• 2007

The main objectives of this study are to investigate the micro-scale energy transfer mechanism for silicon wafer and to find an efficient way for fabrication of silicon wafer through-hole by using the femtosecond pulse laser ablation. In addition, the electron-phonon interactions during laser irradiation are discussed and the carrier number density and temperatures are estimated. In particular, the present study observes the shapes of silicon wafer through-hole with $100\;{\mu}m$ diameter and it also measures the heat-affected area and the ablation depths fur different laser fluences by using the optic microscope and the three-dimensional profile measurement technique. First, from numerical investigation, it is found that the nonequilibrium state exists between electrons and phonons during laser irradiation. From experimental results, it should be noted that the heat-affected area increases with laser fluence, and the optimal conditions for through-hole formation with minimum heat affected zone are finally obtained.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.5
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• pp.137-142
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• 2017

The development of medical devices based on the theory of tranditional Korean medicine is increasing due to population aging and emerging demand for medical services. Various clinical trials are being conducted to ensure the clinical effectiveness of the developed medical devices, and the importance of systematic management of variously collected information in this process is increasing. In this paper, we designed and constructed the database that can systematically manage the medical information of the patient and the pulse measurement information in conducting clinical trials by using pulse analysis system which is a representative diagnostic method of traditional Korean medicine. The constructed database can be efficiently used for the verification of existing algorithms or developing new algorithms through the quality control of various information and measured data on clinical trials. It also has several advantages in the control of clinical data. The results of this study can contribute to the establishment of Korean medical device data standard for the construction of integrated database management system that can share information with different kind of pulse analysis system and other bio-signal measuring devices.

• Journal of the Korea Convergence Society
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• v.9 no.9
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• pp.41-46
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• 2018

Six sigma methodology is the management tools not only can cause productivity enhancement through the quality control and cost reduction of products and services but also can be applied to various activities of corporates such as research and development. Development of high-density information storage media and devices is indispensible to accomplish the information convergence era. In this paper, we report the case of applying six sigma methodology and tools to the development project of high-density information storage media. The standard DMAIC process was applied to the project and pursuing goals and tools and results in each stage were explained in detail. By adopting the methodology, we could establish fabrication methods of information storage media of recording density higher than $250Gb/in^2$ with high uniformity and reproducibility. The magnetic property and performance of fabricated media were confirmed through measurement of the magnetic hysteresis curve.

• Journal of Ocean Engineering and Technology
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• v.11 no.4
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• pp.61-75
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• 1997

The social demand urges us to use some equipments and structures in high temperature environment. By this occasion, the necessity of studying the fatigue crack growth is an important aspect of new materials. However, the present situation is rarely to accumulate the fatigue data. Especially, 1Cr-1Mo-0.25V steel and 304 stainless steel have been increased to be used under the severe condition of high temperature. And so, the fatigue estimation of those materials is important and appropriate. Fatigue tests have been carried out to examine the crack initiation, growth behaviour for the small fatigue crack of 1Cr-1Mo-0.25V steel and 304 stainless steel at room temperature and 538^{\circ}C$. The remote measurement system which has many merits of checking and saving the image for detailed examination was applied to closely detect the crack length. Generally, the fatigue crack initiated in the form of multiple cracks and grew each other. And then it coalesced to become a major crack. The major crack governed the rest of the fatigue life. In the growing process, each peripheral cracks interact and grow for a certain period. After then, it coalesced and fractured. On the basis of the above experimental data for the small crack, a simulation program was developed to predict the residual life time and to estimate the integrity of machine elements and structures. At the same time, the simulation was extended to 1Cr-1Mo-0.25V steel. The simulation results have shown a good agreement to those of the experimental ones for both materials of 1Cr-1Mo-0.25V steel and 304 stainless steel with small cracks. The NASCRAC has applied to compare the fatigue life with the experimental results. And so, it can be said that the simulation program is valuable tools to the industrial fields.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.32-42
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• 2007

The substrate resistance is modeled to estimate the performance degradation of analog circuits by substrate noise in a $0.35{\mu}m$ twin-well non-epitaxial CMOS process. The substrate resistance model equations are applied to the P+ guard-ring isolation structure and a good match was achieved between measurements and models. The substrate resistance is divided into four types and a semi-empirical model equation is obtained for each type of substrate resistance. The rms(root-mean-square) error of the substrate resistance model is below 10% compared with the measured resistance. To apply this substrate resistance model to the P+ guard ring structure, ADS(Advanced Design System) circuit simulation results are compared with the measurement results using Network Analyzer, and relatively good agreements are obtained between measurements and simulations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.1-6
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• 2008

The holding voltage of the high-voltage MOSFETs in snapback condition is much smaller than the power supply voltage. Such characteristics may cause the latcup-like problems in the Smart Power ICs if these devices are directly used in the ESD (Electrostatic Discharge) power clamp. In this work, a latchup-free design based on the Drain-Extended PMOS (DEPMOS) adopting gate VDD structure is proposed. The operation region of the proposed gate-VDD DEPMOS ESD power clamp is below the onset of the snapback to avoid the danger of latch-up. From the measurement on the devices fabricated using a $0.35\;{\mu}m$ BCD (Bipolar-CMOS-DMOS) Process (60V), it was observed that the proposed ESD power clamp can provide 500% higher ESD robustness per silicon area as compared to the conventional clamps with gate-driven LDMOS (lateral double-diffused MOS).

• Journal of IKEEE
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• v.14 no.1
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• pp.33-39
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• 2010

In this paper, a 5Gb/s receiver with an adaptive equalizer for serial link interfaces is proposed. For effective gain control, a least-mean-square (LMS) algorithm was implemented with two internal signals of slicers instead of output node of an equalizing filter. The scheme does not affect on a bandwidth of the equalizing filter. It also can be implemented without passive filter and it saves chip area and power consumption since two internal signals of slicers have a similar DC magnitude. The proposed adaptive equalizer can compensate up to 25dB and operate in various environments, which are 15m shield-twisted pair (STP) cable for DisplayPort and FR-4 traces for backplane. This work is implemented in $0.18-{\mu}m$ 1-poly 4-metal CMOS technology and occupies $200{\times}300{\mu}m^2$. Measurement results show only 6mW small power consumption and 2Gbps operating range with fabricated chip. The equalizer is expected to satisfy up to 5Gbps operating range if stable varactor(RF) is supported by foundry process.

• Journal of IKEEE
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• v.18 no.4
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• pp.559-565
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• 2014

A 3 dB coupler has been designed and implemented using the most commonly used double-sided FR4 boards. The coupling and the bandwidth of the coupler are enhanced with the enlarged overlapped area of the coupler. Major design parameters are plotted as a design guide and the parameters are verified by simulation and measurement. The size of the manufactured coupler is $30{\times}14mm^2$. Its measured insertion loss and phase difference are 0.6 dB and $90.5^{\circ}$ at center frequency of 2.5 GHz, respectively. The operating frequency range is 1.72 GHz to 3.08 GHz for $3.6{\pm}0.5dB$ insertion loss. The coupler has the performance similar to that of conventional Lange coupler, and implementation of the coupler is easy and cheap with wide metal width and spacing and no additional wire bonding process.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.12
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• pp.1367-1374
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• 2008

A new high-gain Fabry-$P{\acute{e}}rot$ cavity antenna for wireless broadband internet(Wibro) base station antennas, which is covered with metamaterial superstrate presenting simultaneous negative values of permittivity and permeability, is proposed. To facilitate the fabrication process using the printed circuit board(PCB) technology of today, a new planar-type metamaterial superstrate is designed, which shows negative and low positive values of a refractive index near the Wibro service frequency band. And the principle of antenna gain enhancement is analyzed from the two different view points of effectively low refractive index and of the Fabry-$P{\acute{e}}rot$ resonance condition. Single square patch antenna is used as a feeder. The separation distance is determined by considering the reflection phases of the metamaterial superstrate and the substrate satisfying Fabry-$P{\acute{e}}rot$ resonance condition, respectively. Comparison between the prediction and the measurement shows good agreement, which verifies the validity of our design approach.