• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1349-1359
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• 1998

In this paper, presented is the result of a digital implementation of a FM stereo composite signal generator. The chip utilizing DDFS(Direct Digital Frequency Synthesizer architecture is implemented using $1.0\mu\textrm{m}$ CMOS gate-array technology thereby replacing analog componentry. To verify the process of generating composite signals a conventional logic simulation method was used. The processed chip was mounted on an evaluation PCB to test and analyze to signals. According to the measurement result obtained by using a 12-bit DAC, the digital FM composite signal generator produces a 74DB spectrally pure signal over its entire tuning range, which is superior to that of analog counterpart by 14dB in it spectral reponse. And further enhancements of the spectral response is expected to be achieved by using a high resolution digital to analog converter, such as a 16-bit DAC. The resulting signals is superior to the signal of the analoy circuitry typically used, in major characteristics such as S/N ratios, accuracy, tuning stability, and signal seperation.

• Journal of the Korea Convergence Society
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• v.11 no.8
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• pp.33-38
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• 2020

Modern society needs to think in new directions and solve problems by grafting problems from diverse fields with computers. Abstraction and automation of various problems using computing technology with your own ideas is called computational thinking. In this paper, we analyze how to diagnose and improve knowledge information based on computational thinking through the process of presenting a variety of problems in programming education situations and finding several problem-solving methods to solve them. To pretest the learners, they were diagnosed using a measurement sheet and a LightBot. By determining the correlation between the evaluation results and LightBot results, the learners' current knowledge statuses were checked, and the correlation between the evaluation results and the LightBot results, based on what was taught according to the problem-solving learning technique, was analyzed according to the proposed technique. The analysis of the group average score of the learners showed that the learning effect was significant. If the method of deriving and improving knowledge based on computational thinking ability for solving the problem proposed in this paper is applied to software education, it will induce student interest, thereby increasing the learning effect.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.11
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• pp.941-948
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• 2009

The present study aims at the examination of the effects of 1 mol% NiO addition on the reaction, microstructure development, resultant electrical properties, and especially the bulk trap and interface state levels of $ZnO-Bi_2O_3-Sb_2O_3$ (Sb/Bi=0.5, 1.0, and 2.0) systems (ZBS). The samples were prepared by conventional ceramic process, and characterized by density, XRD, SEM, I-V, impedance and modulus spectroscopy (IS & MS) measurement. The sintering and electrical properties of Ni-doped ZBS (ZBSN) systems were controlled by Sb/Bi ratio. Pyrochlore ($Zn_2Bi_3Sb_3O_{14}$) was decomposed more than $100^{\circ}C$ lowered in ZBS (Sb/Bi=1.0) by Ni doping. The reproduction of pyrochlore was suppressed by the addition of Ni in ZBS. Between two polymorphs of $Zn_7Sb_2O_{12}$ spinel ($\alpha$ and $\beta$), microstructure of ZBSN (Sb/Bi=0.5) composed of a-spinel was more homogeneous than $Sb/Bi{\geq}1.0$ composed of $\beta$-spinel phase. In ZBSN, the varistor characteristics were not improved drastically (non-linear coefficient $\alpha\;=\;6{\sim}11$) and independent on microstructure according to Sb/Bi ratio. Doping of Ni to ZBS seemed to form ${V_0}^{\cdot}$ (0.33 eV) as dominant bulk defect. From IS & MS, especially the grain boundaries of Sb/Bi=0.5 systems were divided into two types, i.e. sensitive to oxygen and thus electrically active one and electrically inactive intergranular one with temperature.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.66 no.3
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• pp.99-104
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• 2017

The three-phase four-wire power distribution system can be used to supply power to single-phase and three-phase loads at the same time. There are linear loads and nonlinear loads as single-phase loads connected to each phase. The nonlinear load generates a harmonic current during the power energy conversion process. In particular, the single-phase nonlinear load has a higher proportion of generation of the third harmonic current than the harmonics of the other orders. In a three-phase four-wire system, the third harmonic current flows through the neutral wire to the power supply side, affecting the power supply side and the line. Furthermore, the magnitude of the current flowing in the neutral line can be higher than the current flowing in the individual phase. If the neutral current is higher than the phase current, the breaker may be blocked. Therefore, it is necessary to reduce the amount of current flowing in the neutral line by harmonics. There is a method of zigzag connecting a single phase transformer by a method of reducing 3 harmonic current. In this study, the method of reducing the magnitude of the three harmonic currents flowing through the zigzag wire by comparing the polarity and the negative polarity characteristics of the single phase transformer was compared through measurement and simulation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1543-1551
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC(Digital-to-Analog Converter) is employed to overcome the problems of dithering scheme. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The proposed DCO has been designed in a $0.13{\mu}m$ CMOS process. Measurement results shows that the designed DCO oscillates in 2.8GHz~3.5GHz and has a frequency tuning range of 660MHz and a resolution of 73Hz at 2.8GHz band. The designed DCO exhibits a phase noise of -119dBc/Hz at lMHz frequency offset. The DCO core consumes 4.2mA from l.2V supply. The chip area is $1.3mm{\times}1.3mm$ including pads.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1261-1266
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• 2017

A random and systematic jitter suppressed delay locked loop (DLL)-based clock generator with a delay-time voltage variance converter (DVVC) and an averaging circuit (AC) is presented. The DVVC senses the delay variance of each delay stage and generates a voltage. The AC averages the output voltages of two consecutive DVVCs to suppress the systematic and random delay variance of each delay stage in the VCDL. The DVVC and AC averages the delay time of successive delay stages and equalizes the delay time of all delay stages. In addition, a capacitor with a switch working effectively as a negative feedback function is introduced to reduce the variation of the loop filter output voltage. Measurement results of the DLL-based clock generator fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process shows 13.4-ps rms jitter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.39A no.12
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• pp.691-698
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• 2014

An L-band single side band(SSB) mixer with CMOS switches and a C-band quadrature voltage-controlled oscillator(QVCO) have been developed using the TowerJazz 0.18-um RFCMOS process. The SSB mixer exhibits a conversion gain of 6.6 ~ 7.5 dB with a 70-dBc image rejection ratio and 65-dBc port isolation. The oscillation frequency range of the QVCO is 6.2 ~ 6.7 GHz with an output power of 4~6 dBm. For measurement, 1.8 V supply voltage is used while drawing 36 mA for the mixer and 23 mA for the QVCO.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.9B
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• pp.811-820
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• 2006

In this paper, The correlation of the power consumption of sensor node is analyzed according to the analyze parameter in IEEE 802.15.4 star sensor network. And It is studied the influence on analysis parameter. The power consumption of sensor network in transmission process and average transmission power consumption drives to numerical formula. And CSEM WiseNET system measurement value is used. As a simulation result, The power consumption of sensor node in star network consist of 10 sensor nodes is more than 20 % that in single network in average. When beacon signal interval is 0.1 second in all frequency bands, the power consumption of sensor node in up-link is more than 2.5 times that in down-link in average. When beacon signal interval is 1 second and the number of sensor nodes increases to 100 and sensing data increases to 100 byte, the power consumption of sensor node increases to 2.3 times. And The superior performance of 2.4 GHz frequency band has than 868/915 MHz frequency band up to $6{\sim}12$ times.

• The KIPS Transactions:PartD
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• v.13D no.1 s.104
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• pp.61-66
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• 2006

It is reported that the success ratio of software development projects has been only 30%. Many causes lower project's chance of success, particularly lack of systematic project management. Especially, moving on the next phase of project with unsatisfactory outputs can be very problematic because it can cause much waste of resource, time and even lead to the failure of the whole project. Peer review and inspection are some of the practices designed to prevent such waste and possible failure. When defects are identified through such progress, each developer has to work on the product component again and fix the problem. This process is called rework. In this paper, we propose a method for improving quality of reworked product component to prevent excessive cost and time consumed caused by moving on the next phase of a project with a problematic product component. More specifically, this paper suggests a rework indicator that measures the level of rework based on its complexity and severity and is used to choose appropriate checking method on reworked product component. The research also confirmed the method's usefulness and effectiveness by applying the suggested method on four projects.

• Tunnel and Underground Space
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• v.11 no.4
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• pp.352-361
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• 2001

Mode I fracture toughness ( $K_{IC}$) of the frozen rocks and that of the frozen-thawed rocks were obtained by using BDT and CCNBD specimens. The test temperatures ranged from +$25^{\circ}C$ to -16$0^{\circ}C$. Wet and air-dry specimens of granite and sandstone were used in order to investigate the effect of water and porosity on fracture toughness. The SEM images of the frozen-thawed rocks were also analysed to check the density of thermal cracks. The $K_{IC}$ of the frozen rocks increased as the test temperature went down. The rate of increase was higher in wet condition than in dry condition and the rate of increase for wet granite was higher than that for wet sandstone. The $K_{IC}$ of the frozen-thawed rocks varied within 15% from the $K_{IC}$ of the rocks at room temperature. After one freeze-thaw process, thermal crack occurred in granite but no thermal cracks occurred in sandstone. And the crack density was increased as the temperature went down.n.