• Title/Summary/Keyword: process delay

Search Result 1,576, Processing Time 0.028 seconds

Stochastic Stabilization of TS Fuzzy System with Markovian Input Delay (마코프 입력 지연 시스템의 확률적 안정화)

  • Lee, Ho-Jae;Park, Jin-Bae;Lee, Sang-Youn;Joo, Young-Hoon
    • Proceedings of the Korean Institute of Intelligent Systems Conference
    • /
    • 2001.12a
    • /
    • pp.153-156
    • /
    • 2001
  • This paper discusses a stochastic stabilization of Takagi-Sugeno (75) fuzzy system with Markovian input delay. The finite Markovian process is adopted to model the input delay of the overall control system. It is assumed that the zero and hold devices are used for control input. The continuous-time 75 fuzzy system with the Markovian input delay is discretized for easy handling delay, accordingly, the discretized 75 fuzzy system is represented by a discrete-time 75 fuzzy system with jumping parameters. The stochastic stabilizibility of the jump 75 fuzzy system is derived and formulated in terms of linear matrix inequalities (LMls).

  • PDF

Performance Analysis of GCRA Policing Algorithm for Constant-Bit Rate Service (항등비트율 서비스를 위한 GCRA 폴리싱 알고리즘의 성능 해석)

  • Kim, Young-Beom
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.10 no.12
    • /
    • pp.2157-2165
    • /
    • 2006
  • In implementing GCRA, well known as the representative user traffic policing algorithm for constant-bit rate service, it is essential to set proper values for delay variation tolerance in order to prevent network overload and excessive user data loss due to delay variation incurred inevitably during transmission process. In this paper, we investigate the performance of GCRA algorithm for various values of delay variation tolerance and suggest a guideline for setting proper delay variation tolerance values.

A 5-20 GHz 5-Bit True Time Delay Circuit in 0.18 ㎛ CMOS Technology

  • Choi, Jae Young;Cho, Moon-Kyu;Baek, Donghyun;Kim, Jeong-Geun
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.13 no.3
    • /
    • pp.193-197
    • /
    • 2013
  • This paper presents a 5-bit true time delay circuit using a standard 0.18 ${\mu}m$ CMOS process for the broadband phased array antenna without the beam squint. The maximum time delay of ~106 ps with the delay step of ~3.3 ps is achieved at 5-20 GHz. The RMS group delay and amplitude errors are < 1 ps and <2 dB, respectively. The measured insertion loss is <27 dB and the input and output return losses are <12 dB at 5-15 GHz. The current consumption is nearly zero with 1.8 V supply. The chip size is $1.04{\times}0.85\;mm^2$ including pads.

A Study on Simulation Analysis for the Transmission Delay on the Process bus network in IEC 61850 Digital Substation (디지털변전소 통합 IED 용 Process Bus 네트워크 통신지연 시뮬레이션 연구)

  • Kim, Seok-Kon;An, Yong-Ho;Jang, Byung-Tae;Choi, Jong-Kee;Lee, Nam-Ho;Han, Jung-Yeol;Lee, You-Jin
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
    • /
    • v.29 no.8
    • /
    • pp.18-22
    • /
    • 2015
  • Digitalization of the substation in Korea has been in progress so far with focusing on Station Bus. However, its application to Process Bus has been delayed due to some technical issues. IEDs based on Process Bus use the data values of SV and GOOSE. As the size of communication data on Process Bus is comparatively bigger than that of Station Bus, it is very important for the evaluating the performance of Process Bus to analyze the transferring speed and quality of data from the first equipment, which is located on process level, to station level. According to the results of related studies, it is said that the most important factor for the design and operation of Process Bus network is the communication delay with consideration of the volume of packets. In the paper, the results of performance test for the network with and without application of VLAN on Process Bus system that uses integrated IEDs are presented. Additionally, the paper proposes the optimal method to analyze the communication delays of network systems through evaluating the maximum delay time, link process ratio and the amount of lost packets by using a simulation tool.

Real-coded genetic algorithm for identification of time-delay process

  • Shin, Gang-Wook;Lee, Tae-Bong
    • 제어로봇시스템학회:학술대회논문집
    • /
    • 2005.06a
    • /
    • pp.1645-1650
    • /
    • 2005
  • FOPDT(First-Order Plus Dead-Time) and SOPDT(Second-Order Plus Dead-Time) process, which are used as the most useful process in industry, are difficult about process identification because of the long dead-time problem and the model mismatch problem. Thus, the accuracy of process identification is the most important problem in FOPDT and SOPDT process control. In this paper, we proposed the real-coded genetic algorithm for identification of FOPDT and SOPDT processes. The proposed method using real-coding genetic algorithm shows better performance characteristic comparing with the existing an area-based identification method and a directed identification method that use step-test responses. The proposed strategy obtained useful result through a number of simulation examples.

  • PDF

Performance Evaluation of Web-based Cloud Services in a Browser-Scripting Approach

  • Zhang, Chengwei;Hei, Xiaojun;Cheng, Wenqing
    • KSII Transactions on Internet and Information Systems (TIIS)
    • /
    • v.10 no.6
    • /
    • pp.2463-2482
    • /
    • 2016
  • Cloud services are often provisioned to their customers using user-friendly web browsers with flexible and rich plug-in environments. Delay is one of the fundamental performance metrics of these web-based services. Commonly-used network measurement tools usually only measure network delay and it may be difficult to infer the web-delay performance using only network layer measurement approaches. In this paper, we propose to evaluate the application layer delay in a browser-based network measurement platform using engineered scripts. We conducted a delay measurement study using instrumented scripts in the proposed browser-based measurement platform. Our investigation included a comparison study of three browser-scripting delay measurement methods, including Java applet, JSP and Flash ActionScript. We developed a browser-based delay measurement testbed over the Internet so that different delay measurement tools could be evaluated in the same real network environment including typical Internet paths and the Baidu cloud. We also decomposed the components of the end-to-end delay process of the above measurements to reveal the difference and relationship between the network-layer delay and the application-layer delay. Our measurement results characterize the stochastic properties of the application-layer delay over real Internet paths, and how these properties vary from the underlying network layer delay. This browser-scripting measurement approach can be easily deployed on different cloud service platforms to inspect their application-layer delay performance between end clients and the cloud platforms. Our measurement results may provide insights into designing new cloud services with enhanced quality-of-experience perceived by cloud users.

Fuzzy Self-Organizing Control of Environmental Temperature Chamber (온도챔버의 퍼지 자동조정 제어시스템)

  • 김인식;권오석
    • Journal of the Korean Institute of Telematics and Electronics B
    • /
    • v.31B no.1
    • /
    • pp.34-40
    • /
    • 1994
  • The design and implementation of a fuzzy self-organizing controller for an environmental temperature chamber is discussed. The chamber is a non-linear, time-variant system with delay-time and dead-time. And the parameter tuning is required in PI control when the performance degraded. However the proposed fuzzy-SOC monitors the performance of the process. modifies the data base, and performs the delay-time compensation based on the idealized process model. A series of experiments was performed for the conventional PI and the fuzzy-SOC. These experimental results show the usefulness of the fuzzy-SOC.

  • PDF

An Improved Timing-level Gate-delay Calculation Algorithm (개선된 타이밍 수준 게이트 지연 계산 알고리즘)

  • Kim, Boo-Sung;Kim, Seok-Yoon
    • Journal of the Korean Institute of Telematics and Electronics C
    • /
    • v.36C no.8
    • /
    • pp.1-9
    • /
    • 1999
  • Timing-level circuit analyses are used to obtain fast and accurate results, and the analysis of gate and interconnect delay is necessary to validate the correctness of circuit design. This paper proposes an efficient algorithm which simultaneously calculates the gate delay and the transition time of linearized voltage source for subsequent interconnect delay calculation. The notion of effective capacitance is used to calculate the gate delay and the transition time of linearized voltage source which considers the on-resistance of driving gate. The procedure for obtaining the gate delay and the transition time of linearized voltage source has been developed through an iterative operation using the precharacterized data of gates. While previous methods require extra information for the transition time calculation of linearized voltage sources, our method uses the derived data during the gate delay calculation process, which does not require any change in the precharacterization process.

  • PDF

A study on the receive buffer control schemes for bobile multimedia services (이동 멀티미디어 서비스를 위한 수신버퍼 제어에 관한 연구)

  • 이태훈;김용득
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.23 no.4
    • /
    • pp.940-949
    • /
    • 1998
  • The paper proposes an effective mechanism hiring the adaptive buffer control schemes on the mobile seceiver's side that can resolve the problems of delay spikes caused by the handover process onthe cell boundaries when they transmit real-time moving images through the high speed wireless channels. to confirm the effectiveness of the proposed schemes, we have modeled the characteristics of the random errors on the wireless channels, the burst errors and that of the transmission delay by the handover. We also compared the rate of the delay-adaptation of the receive buffers caused by the delay and delay spikes. the comparison was done by testing the suggested schemes against the existing schemes by applying tehm to the packet delay model. We also could identify the noticable reduction of the casesof buffer delay and overflow compared with the conventional schemes, by applying the suggested algorithm to the video image compressed by H.263.

  • PDF

Critical Factors Causing Delay on State-Funded Construction Projects in Vietnam

  • Luu, Van Truong;Kim, Soo-Yong;Pham, Nguyen-The-Thanh;Nguyen, Thanh-Long;Nguyen, Tuan-Kiet
    • International conference on construction engineering and project management
    • /
    • 2015.10a
    • /
    • pp.104-108
    • /
    • 2015
  • Delay on State-Funded Construction Projects (SFCPs) in Dong Thap - a province in Mekong Delta of Vietnam, as many provinces of Vietnam, have caused budget overrun through many recent years. The budget-overrun situations, in turn, have deepened the delay. Identifying critical factors affecting delay SFCPs plays a key role to mitigate negative impact of delay. 134/160 questionnaires were collected from personals working for project owners, consultants, supervisors and contractors in Dong Thap Province. Convenient sampling method was used. EFA was resulted in critical 04 factors with 20 variables caused delay in SFCPs, including: "Project technic, contractor's financial capacity and adjustment role of the government", "Regulation and Policy", "Mutual benefit support and concern between the government and residents", and "Disadvantage of construction site and weather season". Reliable measures to reduce delay on SFCPs are discussed to establish legal corridors to strictly controlling the process, consider mutual benefit between the government and its residents, and evaluating construction conditions. Those measures are considered could be applied in not only Dong Thap province, but most provinces of Vietnam as well.

  • PDF