• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05a
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• pp.28-31
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• 2004

A Quadrature phase detector for high-speed delay-locked loop is introduced. The proposed Quadrature phase detector is composed of two nor gates and it determines if the phase difference of two input clocks is 90 degrees or not. The delay locked loop circuit including the Quadrature phase detector is fabricated in a 0.18 urn standard CMOS process and it operates at 5 ㎓ frequency. The phase error of the delay-locked loop is maximum 2 degrees and the circuits are robust with voltage, temperature variations.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.1
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• pp.52-59
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• 1987

A new on-line estimation algorithm for a time varying time delay is proposed. This algorithm is based on the concept of minimization of prediction error. As only the parameters directly related to the poles and zeros of the process are estimated in the algorithm, persistently exciting condition for the convergence of parameters can be less restrictive. Under some assumptions which is necessary in adaptive control, it is shown that this algorithm estimates time varying time delay accurately. In view of computational burden, this algorithm needs far less amount of calculations than other methods. The larger the time delay is, the more effective this algorithm is . Computer simulation shows good properties of the algorithm. This algorithm can be used effectively in adaptive control of large dead time processes.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1838-1842
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• 2004

Gain and phase margins of a first order plus delayed time (FOPDT) process controlled by generalized predictive controller (GPC) are related to the control parameters ${\lambda}$ (control move suppression parameter) and ${\alpha}$ (smoothing filter coefficient) and the normalized delay of the process. Variation ranges of gain and phase margins are determined. It is shown that the margins cannot be assigned independently for a wide range of variation and the range is narrowing by increase of the normalized delay of the process. And finally curves are given to use for adjustment of the controller parameters in order to obtain a specific pair of gain and phase margins.

• 제어로봇시스템학회:학술대회논문집
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• 1993.10b
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• pp.406-411
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• 1993

A variable structure control scheme that can be applied to the process with input/output delays are proposed and its control performances are evaluated. The proposed VSCS, which is an output fedback scheme, comprises an integrator for tracking the setpoint and the Smith predictor for compensating the effects of time delay. With The VSCS, the robustness against the parameter variations and external disturbances can be achieved even when the controlled process includes I/O delays. And the desired transient response is obtained by simple adjustment of the coefficients of the switching surface equation.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.106-108
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• 2005

The calculation of parameters of a process model is modified to find that better sliding mode controller for a process with time delay. A design method by Camacho has such problems as chattering, overshoot due to the Pade approximation errors for the time delay term of the first order model. In this paper, a new design technique for a sliding mode controller is proposed by introducing the modified Pade approximation considering the weight factor. The modified method is expected to provide a more accurate model with better control settings.

• Journal of Institute of Control, Robotics and Systems
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• v.20 no.7
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• pp.750-755
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• 2014

Product shortage which causes backordering and/or lost sales cost is very popular in chemical industries, especially in commodity polymer business. This study deals with backordering cost in the supply chain optimization model under the framework of process-inventory network. Classical economic order quantity model with backordering cost suggested optimal time delay and lot size of the final product delivery. Backordering can be compensated by advancing production/transportation of it or purchasing substitute product from third party as well as product delivery delay in supply chain network. Optimal solutions considering all means to recover shortage are more complicated than the classical one. We found three different solutions depending on parametric range and variable bounds. Optimal capacity of production/transportation processes associated with the product in backordering can be different from that when the product is not in backordering. The product shipping cycle time computed in this study was smaller than that optimized by the classical EOQ model.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.373-375
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• 1997

In this study, we designed multiple mesh circuit consisting of 3-6 meshes and pulse superposition one consisting of a 3 mesh, and fabricated the electrical power supply and the single elliptical resonator. We developed the two pulse superposition technique forming the step pulse shapes of pulsed Nd:YAG laser with single shot multivibrator and 2 SCRs. Laser beam generated by multiple mesh circuit and superposition one respectively irradiated target surface to analyze process state of surface with spark and vapor. And it was obtained experimental results that all superposition meshes had common points which the best efficiency was obtained at delay time 0[${\mu}s$], followed by, no superposition and obtained at delay time 250[${\mu}s$].

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.731-733
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• 1988

This paper describes a design of hardware system for real time automatic diagnosis of ECG arrhythmia based on pipeline processor consisting of the three microcomputer. ECG data is acquisited by 12 bit A/D converter with hardware QRS triggered detector. Four diagnostic parameters - heart rate, morphology, axis, and ST segment - are used for the classification and the diagnosis of arrhythmia. The functions of the main CPU were distributed and processed with three microcomputers. There-fore the effective data process and the real time process using microcomputer can be obtained. The interconnection structure consisting of two common memory units is designed to decrease the delay time caused by data transfer between processors and by which the delay time can be taken 1 % of one clock period.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.11
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• pp.619-625
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• 2003

We proposed an optimum PID controller design method of the Smith Predictor It can be applied to various processes. The real process is approximated via the second order plus time delay model (SOPTD) whose parameters are specified through a model reduction algorithm. We already proposed a new model reduction method that considered four point in the Nyquist curve to reduced the steady state error between the real process model and the reduced model using the gradient decent method and the genetic algorithms. In addition, the Smith predictor is used to compensate time delay of the real process model. In this paper, the new optimum parameter tuning algorithm for PID controller of the Smith Predictor is proposed through ITAE as performance index. The Simulation results show the validity and improvement of performance for various processes.

• Journal of the Korea Society of Computer and Information
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• v.20 no.9
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• pp.1-10
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• 2015

In this paper, we propose a new variable latency L1 data cache architecture for multi-core processors. Our proposed architecture extends the traditional variable latency cache to be geared toward the multi-core processors. We added a specialized data structure for recording the latency of the L1 data cache. Depending on the added latency to the L1 data cache, the value stored to the data structure is determined. It also tracks the remaining cycles of the L1 data cache which notifies data arrival to the reservation station in the core. As in the variable latency cache of the single-core architecture, our proposed architecture flexibly extends the cache access cycles considering process variation. The proposed cache architecture can reduce yield losses incurred by L1 cache access time failures to nearly 0%. Moreover, we quantitatively evaluate performance, power, energy consumption, power-delay product, and energy-delay product when increasing the number of cache access cycles.