• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.32 no.5
• /
• pp.430-436
• /
• 2008

This paper proposes a way to predict electrical lifetime of a relay using Accelerated Life Testings (ALTs). The relay of interest mounting on printed circuit boards is usually under an inrush current stress. The inrush current is generated and accelerated through controlling a lamp switching device in the ALT. We find that the dominant failure mechanism under high levels of inrush current would be contact welding in the contact surface of the relay and the contact welding process is accelerated according to increase in inrush current. The electrical lifetime model based on Inverse Power Law in term of inrush current is proposed, and parameters characterizing relay's lifetime distribution are statistically estimated using ALTA 6 PRO software.

• International Journal of Precision Engineering and Manufacturing
• /
• v.9 no.2
• /
• pp.50-53
• /
• 2008

A design approach using a one-dimensional (1D) lumped model was studied and applied to an industrial inkjet printing head design for micro patterning on printed circuit boards. For an accurate analysis, a three-dimensional piezoelectric-driven actuator model was analyzed and its jetting characteristics were applied to 1Danalysis model. The performance of the 1D lumped model was verified by comparing measured and simulated results. The developed 1D model helped to optimize the design and configuration of the inkjet head and could be implemented in the design of multi-nozzle inkjet printing heads to improve the jetting frequency and minimize crosstalk.

• Journal of Welding and Joining
• /
• v.15 no.6
• /
• pp.105-115
• /
• 1997

A numerical study is performed to predict the thermal response of a detailed card assembly during infrared reflow soldering. The card assembly is exposed to discontinuous infrared panel heater temperature distributions and high radiative/convective heating and cooling rates at the inlet and exit of the oven. The convective, radiative and conduction heat transfer within the reflow oven as well as within the card assembly are simulated and the predictions illustrate the detailed thermal responses. The predictions show that mixed convection plays an important role with relatively high frequency effects attributed to buoyancy forces, however the thermal response of the card assembly is dominated by radiation. The predictions of the detailed card assembly thermal response can be used to select the oven operating conditions to ensure proper solder melting and minimization of thermally induced card assembly tresses and warpage.

• Journal of the Korean institute of surface engineering
• /
• v.49 no.6
• /
• pp.477-485
• /
• 2016

As expensive and valuable metals being used in electronic and semiconducting industries are abandoned as industrial wastes after use of them, it is required to recover them from e-wasted electronics parts. Gold which is used for printed circuit boards or electronic equipments, accessories, etc., is one of e-Wasted materials and recently indium, gallium, zirconium, cobalt, molybdenum and lithium are bacome valuable metals to be recovered from the e-wastes. Since the amount of precious metals is now being faced with scarcity, lean too much on area and instability of supply, and industrial demands are rapidly increasing every year, it becomes more important to recover the valuable metals from the industrial wastes. In this review, we introduced technologies and research trend of the recovery processes of valuable metals from the e-wastes in high-tech devices over the world.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.55 no.12
• /
• pp.597-600
• /
• 2006

When the energy of the nanoseconds high voltage pulse with hundreds picoseconds of the pulse rise time is emitted into the free space via an antenna, an ultra wide band electromagnetic wave is generated. This electromagnetic wave is expected to be used in transmitting vast amount of informations to far distance, high performance radars, post-packaging pasteurization of food, the detection of underground buried objects, searching of underground water veins or caves, the treatment of waste water or polluted gases and so forth. Additionally, this technology can be used in EMI(electromagnetic interference) evaluation of measuring instruments or printed circuit boards.

• Journal of the Korean Society for Precision Engineering
• /
• v.15 no.7
• /
• pp.26-35
• /
• 1998

This paper presents a visual inspection algorithm looking for solder joint defects of IC chips on PCBs (Printed Circuit Boards). In this algorithm, seven features are proposed in order to categorize the solder joints into four classes such as normal, insufficient, excess, and no solder, and optimal back-propagation network is determined by error evaluation which depend on the number of neurons in hidden and out-put layers and selection of the features. In the end, a good accuracy of classification performance, an optimal determination of network structure and the effectiveness of chosen seven features are examined by experiment using proposed inspection algorithm.

• Journal of Advanced Navigation Technology
• /
• v.28 no.2
• /
• pp.246-249
• /
• 2024

In this paper, we present a miniaturized differential line (DL) using inductance-enhanced corrugated ground planes (LCGP) for effective common-mode (CM) noise suppression in high-speed packages and printed circuit boards. The LCGP-DL demonstrates the CM noise suppression in the frequency range from 2.09 GHz to 3.6 GHz. Furthermore, to achieve the same low cutoff frequency, the LCGP-DL accomplishes a remarkable 23.2% reduction in size compared to a reference DL.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.5
• /
• pp.74-82
• /
• 2015

As the complexity of an electronic device and the reduction of its operating voltage is progressing, susceptibility test of the chip and module for internal or external noises is essential. Although the immunity compliance of the chip was served with IEC 62132-4 Direct Power Injection method as an industry standard, in fact, EM immunity of the chip is influenced by their Power Domain Network (PDN). This paper evaluates the EM noise tolerance of a PLL and compares their noise transfer characteristics to the PLL on various PCB boards. To make differences of the PDNs of PCBs, various PCBs with or without LDO and with several types of capacitors are tested. For evaluation of discrepancies between EM characteristics of an IC only and the IC on real boards, the analysis of the noise transfer characteristics according to the PDNs shows that it gives important information for the design having robust EM characteristics. DPI measurement results show that greatly improved immunity of the PLL in the low-frequency region according to using the LDO and a frequency change of the PLL according to the DPI could also check with TEM cell measurement spectrum.

• Journal of the Microelectronics and Packaging Society
• /
• v.16 no.2
• /
• pp.43-50
• /
• 2009

Although thin PCBs(Printed Circuit Boards) have recently been required for high density interconnection, high electrical performance, and low manufacturing cost, the utilization of thin PCBs is severely limited by warpage and reliability issues. Warpage of the thin PCB leads to failure in solder-joints and chip. The $B^2it$(Buried Bump Interconnection Technology) for PCB has been developed to achieve a competitive manufacturing price. In this study, chip temperature, package warpage, chip stress and solder-joints stress characteristics of the PCB prepared with $B^2it$ process have been calculated using thermo-mechanical coupled analysis by the FEM(Finite Element Method). FEM computation was carried out with the variations in bump shapes and kinds of materials under 1.5W power of chip and constant convection heat transfer. The results show that chip temperature distribution reached more quickly steady-state status with PCB prepared with $B^2it$ process than PCB prepared with conventional via interconnection structure. Although $B^2it$ structures are effective on low package warpage and chip stress, with high strength bump materials arc disadvantage for low stress of solder-joints. Therefore, it is recommended that optimized bump shapes and materials in PCB design should be considered in terms of reliability characteristics in the packaging level.

• Journal of the Korean Society of Safety
• /
• v.30 no.4
• /
• pp.32-38
• /
• 2015

In this paper, we analyzed the vehicle fire accidents due to damage of vehicle's electrical components, which is applied to a vehicle. In recent development of electrical components technology, approximately 40% of vehicle manufacturing parts have applied electronic circuit technology. Phenomenon such deterioration of insulating performance or electric breakdown on the vehicle's electrical components and printed circuit boards(PCBs) resulted from moisture, contamination and aging due to repetitive operations, lead to the vehicle fire. Therefore, the application of electrical components with adequate electric capacity for vehicle and usage of molding techniques using a non-combustible materials to shut off the oxygen should be applied in order to prevent vehicle fire due to damage of the electrical components and PCBs.