• 생물정신의학
• /
• 제21권4호
• /
• pp.168-174
• /
• 2014

Objectives Sensory gating dysfunctions in patients with schizophrenia and bipolar disorder have been investigated through two similar methods ; P50 suppression and prepulse inhibition paradigms. However, recent studies have demonstrated that the two measures are not correlated but rather constitute as distinct neural processes. Recent studies adopting spectral frequency analysis suggest that P50 suppression reflects the interaction between gamma and other frequency bands. The aim of the present study is to investigate which frequency component shows more significant interaction with gamma band. Methods A total of 108 mood disorder patients and 36 normal subjects were included in the study. The P50 responses to conditioning and test stimuli with an intra-pair interval of 500 msec were measured in the study population. According to P50 ratio (amplitude to the test stimulus/amplitude to the conditioning stimulus), the subjects with P50 ratio less than 0.2 were defined as suppressed group (SG) ; non-suppressed group (NSG) consisted of P50 ratio more than 0.8. Thirty-five and 25 subjects were included in SG and NSG, respectively. Point-to-point correlation coefficients (PPCCs) of both groups were calculated between two time-windows : the first window (S1) was defined as the time-window of one hundred millisecond after the conditioning auditory stimulus and the second window (S2) was defined as the time-window of 100 msec after the test auditory stimulus. Spectral frequency analysis was performed to investigate which frequency band results in the difference of PPCC between SG and NSG. Results Significant reduction of PPCC between S1 and S2 was observed in the SG (Pearson's r = 0.24), compared to PPCC of the NSG (r = 0.58, p < 0.05). In spectral frequency analysis, gamma band showed "phase-reset" and similar responses after the two auditory stimuli in suppressed and non-suppressed group. However in the case of alpha band, comparison showed significantly low PPCC in SG (r = -0.14) compared to NSG (r = 0.36, p < 0.05). This may be reflecting "phase-out" of alpha band against gamma band at approximately 50 msecs after the test stimulus in the SG. Conclusions Our study suggests that normal P50 suppression is caused by phase-out of alpha band against gamma band after the second auditory stimulus. Thus it is demonstrated that normal sensory gating process is constituted with attenuated alpha power, superimposed on consistent gamma response. Implications of preserved gamma and decreased alpha band in sensory gating function are discussed.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제16권6호
• /
• pp.745-753
• /
• 2016

This paper presents a fully synthesizable low power interconnect bus for millimeter-scale wireless sensor nodes. A segmented ring bus topology minimizes the required chip real estate with low input/output pad count for ultra-small form factors. By avoiding the conventional open drain-based solution, the bus can be fully synthesizable. Low power is achieved by obviating a need for local oscillators in member nodes. Also, aggressive power gating allows low-power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with a power management unit that has nW standby mode. A 3-module system including the bus is fabricated in a 180 nm process. The entire system consumes 8 nW in standby mode, and the bus achieves 17.5 pJ/bit/chip.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2008년도 하계종합학술대회
• /
• pp.607-608
• /
• 2008

Locking time of the DLL is the important design issue in case of clock gating for low power system. For precise analysis of the locking speed of the DLL, this paper analyzes the locking process of the DLL in time domain. Analysis result shows that the value of the DLL bandwidth over reference frequency should be limited to below 1 ($i.e.w_n/F_{REF}<1$) for the stable operation and relation between bandwidth and lock time is expressed by log function.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 1999년도 하계종합학술대회 논문집
• /
• pp.381-384
• /
• 1999

In this paper, we addressed the problem of reducing the switching activity in pipeline datapath and proposed a solution. clock-gating method is a kind of practical technique for reducing switching activity in finite state machine. But, in the case that the target gated function unit has a pipeline structure, there is some spurious switching activity on each stage register group. This occur in early stage of every function enable cycle. In this paper we proposed a method to solve this problem. This method generates the enable signal to each pipeline stage to gate the clock feeding register group. Experimental results showed effective reduction of dynamic powers in pipeline circuits.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1996년도 하계학술대회 논문집 C
• /
• pp.1547-1549
• /
• 1996

The electrical and optical switching characteristics of gold-doped silicon p-i-n diodes have been investigated. The device shows a dark switching voltage of about 500 V. The switching voltage decreases rapidly when the illumination level is increased. The differential sensitivity of optical gating over linear region is $d(V_{Th}/V_{Tho})/dP_{Ph}$=0.25/uW. The turn-on delay time and the turn-on rise time decrease with increasing optical pulse power. The turn-off delay and the fall time are negligible.

• 한국조명전기설비학회:학술대회논문집
• /
• 한국조명전기설비학회 2000년도 학술대회논문집
• /
• pp.94-98
• /
• 2000

This paper describes an application of the partial discharge measuring method in operating transformer. In the operating transformer, the useful PD signal may be superimposed by radio intereference voltage and impulse shaped noise signals generated by external corona or power electronics. In this paper, initial investigations after connecting the PD measuring system to the terminals of the measuring impedance showed a very high noise level of 3,700pC due to sinusoidal interferences. In order to reject these noises, this paper applied RIV and band-pass filters and noise gating method. The resulting measuring sensitivity was improved from 3,700pC to 160pC.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2007년도 하계학술대회 논문집
• /
• pp.400-402
• /
• 2007

This paper presents a vector control implementation for PMSM using Real Time Workshop and Embedded Target for TI C2000 DSP in MATLAB/SIMULINK. Speed, current and vector controllers are easily designed and implemented by using the MATLAB/SIMULINK program. Feedback of motor speed is processed through C28x QEP(Quadrature Encoder Pulse) block from encoder pulse. 3-Phase currents ares processed through C28x ADC block from current sensors. And gating signal of PWM inverter is generated through SVPWM and PWM block. Real-time program is drawn using SIMULINK and then converted program code for speed control of PMSM is downloaded into the TI eZdsp 2812 board. Experiments were carried out to examine validity of the proposed vector control implementation.

• 융합신호처리학회논문지
• /
• 제3권3호
• /
• pp.70-75
• /
• 2002

본 논문은 새로운 단일 전력단 역률보상 풀 브리지 컨버터를 제안하였다. 제안된 컨버터는 역률보상을 위하여 앞단에 2개의 인덕터, 2개의 다이오드, 2개의 자성결합 변압기를 가진 2VS 풀브리지 DC/DC 컨버터로 구성되어 있다. 이러한 구성방법에 의해 전력은 전원에서 분리되고, 안정된 직류출력전압을 얻을 수 있다. 이 토폴로지에서 주소자의 전압스트레스는 영전압스위칭에 의해서 감소되며, 또한 제안된 컨버터는 능동 역률보정 스위치와 제어 및 게이팅 보드와 같은 보조회로가 필요치 않게되어 규격과 단가를 낮출 수 있을 뿐 아니라 효율을 증가시킬 수 있다.

• 전력전자학회논문지
• /
• 제22권2호
• /
• pp.166-174
• /
• 2017

This study proposes a compensation method for the dead-time effects on a single-phase grid-connected inverter. Dead time should be considered in the pulse-width modulation gating signals to prevent the simultaneous conduction of switching devices, considering that a switching device has a finite switching time. Consequently, the output current of the grid-connected inverter contains odd-numbered harmonics because of the dead time and the nonlinear characteristics of the switching devices. The effects of dead time on output voltage and current are analyzed in this study. A new compensation algorithm based on second-order generalized integrator is also proposed to reduce the dead-time effect. Simulation and experimental results validate the effectiveness of the proposed compensation algorithm.

• 전력전자학회논문지
• /
• 제7권4호
• /
• pp.332-338
• /
• 2002

토카막 장치의 초전도 코일에 사용되는 전원 공급장치는 초대형급(20kA) 직류 전원 공급기로서 빠른 전류제어 응답성과 매우 작은 정상상태 리플이 필수적이다. 특히 역전류 공급이 가능한 회생형 컨버터의 운전중 전류 방향이 바뀌는 순간에도 전류기준값을 잘 추종하는 것이 중요하다. 이러한 조건들을 만족시키기 위하여 입력측에 2중 출력($\Delta$, Y)를 갖는 변압기와 출력단에 상간변압기(interphase transformer, IPT)를 이용한 12펄스 싸이리스터 듀얼 컨버터를 설계, 제작하였다. 각 컨버터에서 출력되는 전류의 합이 부하전류 지령치를 따르도록 제어하는 동시에 차 전류의 평균값이 영이 되도록 함으로써 각 컨버터의 부하 분담율을 일정하게 하여 상간 변압기의 포화를 방지한다. 대전류 코일 전류 공급장치의 양방향 전류 제어 성능을 높이기 위하여 위상각 검출 및 게이팅 지연각 구현을 디지털화하고 컨버터 전류방향 정역절환시 초기 응답특성을 개선하는 방법을 제안하였다. 또한 시뮬레이션과 실부하 전류실험을 통해 제안된 제어기의 동작성능을 확인하였다.