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MBus: A Fully Synthesizable Low-power Portable Interconnect Bus for Millimeter-scale Sensor Systems

  • Lee, Inhee (Department of Electrical Engineering and Computer Science, University of Michigan) ;
  • Kuo, Ye-Sheng (Department of Electrical Engineering and Computer Science, University of Michigan) ;
  • Pannuto, Pat (Department of Electrical Engineering and Computer Science, University of Michigan) ;
  • Kim, Gyouho (Department of Electrical Engineering and Computer Science, University of Michigan) ;
  • Foo, Zhiyoong (Department of Electrical Engineering and Computer Science, University of Michigan) ;
  • Kempke, Ben (Department of Electrical Engineering and Computer Science, University of Michigan) ;
  • Jeong, Seokhyeon (Department of Electrical Engineering and Computer Science, University of Michigan) ;
  • Kim, Yejoong (Department of Electrical Engineering and Computer Science, University of Michigan) ;
  • Dutta, Prabal (Department of Electrical Engineering and Computer Science, University of Michigan) ;
  • Blaauw, David (Department of Electrical Engineering and Computer Science, University of Michigan) ;
  • Lee, Yoonmyung (Department of Semiconductor Systems Engineering, Sungkyunkwan University)
  • Received : 2016.01.07
  • Accepted : 2016.09.06
  • Published : 2016.12.30

Abstract

This paper presents a fully synthesizable low power interconnect bus for millimeter-scale wireless sensor nodes. A segmented ring bus topology minimizes the required chip real estate with low input/output pad count for ultra-small form factors. By avoiding the conventional open drain-based solution, the bus can be fully synthesizable. Low power is achieved by obviating a need for local oscillators in member nodes. Also, aggressive power gating allows low-power standby mode with only 53 gates powered on. An integrated wakeup scheme is compatible with a power management unit that has nW standby mode. A 3-module system including the bus is fabricated in a 180 nm process. The entire system consumes 8 nW in standby mode, and the bus achieves 17.5 pJ/bit/chip.

Keywords

References

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